Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-11-15
2004-01-06
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C713S400000, C713S600000, C710S020000, C326S022000, C326S094000
Reexamination Certificate
active
06675331
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to digital circuitry, and, more particularly, to a testable transparent latch and a method for testing logic circuitry that includes a transparent latch.
BACKGROUND OF THE INVENTION
In the field of digital electronics, a latch is a logic element or device that stores the logic state of its output when a clock or other input is low, and that permits input signals to propagate through the device transparently when the a clock or other input is high. When the clock input is high, the latch acts as a buffer or flow-through logic circuitry, permitting the input signals to propagate freely to the output of the device. When the clock input goes low, the latch stores the logic state of its output, even if one or more logic states at the input of the device have changed during the period that the clock input to the device is low. When the clock input changes from low to high, the logic signals at the input of the device begin to propagate through the device and the device again acts like a buffer or flow-through logic circuitry.
An edge-triggered latch is a latch whose input is sampled at the time of a rising or falling edge on the input clock. In the case of a rising edge-triggered latch, the input of the latch would only be sample for propagation to the output on a rising edge of the clock. Transparent latches are preferred over edge-triggered latches as components of logic circuitry because of the smaller size and higher performance characteristics of transparent latches. Transparent latches are also useful in logic circuitry because transparent latches can alleviate delays in logic circuitry that are introduced by a series of edge-triggered flip-flops. Transparent latches, however, often have poor testability characteristics.
The logic circuitry of integrated circuits is tested for manufacturing defects. During testing, a multiplexer in the integrated circuit switches some of the inputs of the flow-through logic circuitry to testing circuitry for testing the logic circuitry, while the other inputs of the flow-through logic circuitry remain connected to the outputs of the edge-triggered latches, as they are during non-test operation. Other multiplexers switch the inputs of the edge-triggered latches to the outputs of neighboring edge-triggered latches, so that the edge-triggered latches form a chain. For the inputs that are switched to the testing circuitry, the inputs are supplied by the testing circuitry. For the inputs that are connected to the outputs of the edge-triggered latches, the chain of latches is clocked repeatedly, so that a logic state can be loaded onto each latch output by applying those states serially to the input of the first latch in the chain. In this manner, the logic states at all the inputs of the flow-through logic circuitry can be controlled and allowed to propagate through the flow-through logic circuitry.
The outputs of the logic circuitry can be read and compared to the outputs predicted by the a computer simulation of the operation of the logic circuitry. In the case of flow-through logic outputs that can propagate to the testing circuitry, these outputs are read by the testing circuitry. In the case of flow-through logic outputs that are connected to edge-triggered latches, the multiplexers switch the latch inputs back to the flow-through logic and a single clock edge is applied to the logic circuitry to cause the latches to capture the states of the outputs. The multiplexers then switch the latch inputs back so that the latches form a chain again. The logic circuitry is then clocked repeatedly so that the outputs can be read serially from the output of the last latch in the chain.
As compared with edge-triggered latches or flow-through logic circuitry, transparent latches are difficult to control during the testing process. Because the output of a transparent latch is dependent on the state of a clock input, rather than on an edge of a clock input, a transparent latch does not behave like an edge-triggered flip-flop or flow-through logic circuitry during testing. Further, most testing schemes assume that all logic circuitry on the integrated circuit is edge-triggered or flow-trough logic circuitry. Because the propagation of logic signals through a transparent latch is dependent on the logic state of a clock input, it is difficult to measure the output of a logic circuit by controlling the inputs to a transparent latch. As such, testing schemes that test logic circuitry by controlling the inputs to the logic circuitry and comparing the outputs against predicted outputs are not suitable for transparent latches.
SUMMARY OF THE INVENTION
In accordance with the present invention, a transparent latch and a method for testing a transparent latch are provided that substantially eliminate or reduce disadvantages and problems associated with prior transparent latches and testing schemes for transparent latches.
A transparent latch is often included as a component of the logic circuitry of an integrated circuit. The transparent latch that is described herein includes a testing signal and a clock signal. When the testing signal indicates that the logic circuitry is in a testing mode, the transparent latch acts as a buffer or flow-through logic circuitry. When the testing signal indicates that the logic circuitry is not in a testing mode, the transparent latch behaves as a transparent latch, latching or holding the output signal when the clock signal is in a first logic state and permitting the input signal to propagate to the output when the clock signal is an opposite logic state.
A technical advantage of the present invent is a transparent latch that is testable according to existing logic circuitry testing methodologies. Because testing methodologies exist for flow-through logic circuitry, when the transparent latch is in testing mode and caused to act as a buffer or flow-through logic circuitry, the transparent latch is testable. As such, new testing methodologies need not be developed to accommodate the functionality of the transparent latch. Thereby, a given level of test coverage can be achieved with less time and effort in the development and application of test vectors.
Another technical advantage of the present invention is the provision of a testable transparent latch that does not markedly increase the number of transistors from that of a standard transparent latch. The transparent latch of the present invention is made testable with the addition of only a few transistors to the design of a transparent latch. The transparent latch of the present invention is also advantageous in that it does not markedly reduce the performance from that of a standard transparent latch. Further, the transparent latch of the present invention can be incorporated into an existing design that includes a transparent latch without causing a significant delay in the design of the logic circuitry.
Another technical advantage of the present invention is that logic circuitry that includes a transparent latch as described herein is made more dependable and predictable. Because a testable transparent latch of the type described herein is testable according to existing testing schemes, logic circuitry that includes transparent latches can be tested and verified to a greater degree of accuracy and predictability.
REFERENCES:
patent: 5539337 (1996-07-01), Taylor et al.
patent: 6334163 (2001-12-01), Dreps et al.
patent: 6542999 (2003-04-01), Dreps et al.
Dang Lich X
Love Andrew M.
Brady III W. James
Marshall, Jr. Robert D.
Moise Emmanuel L.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Testable transparent latch and method for testing logic... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Testable transparent latch and method for testing logic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Testable transparent latch and method for testing logic... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3240346