Testable programmable gate array and associated LSSD/determinist

Details Testable programmable gate array and associated LSSD/determinist Testable programmable gate array and associated LSSD/determinist

1998-10-28

2000-02-01

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

39550017, G01R 3128

Patent

active

060215135

ABSTRACT:
A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.

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Eichelberger, E. & Williams, T., "A Logic Design for LSI Testability," The Proceedings o fthe 14th Design Automation Conference, pp. 206-211, 1997.

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