Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-12-02
2001-12-25
DeCady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06334200
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the testability design of integrated circuits, and particularly to the testability design of integrated circuits containing a controller or other sequential circuit programmed as a finite state machine at the register transfer level.
2. Description of the Related Art
Integrated circuit (IC) logic devices are subjected to function tests after manufacture to check for faults. Faults are detected by applying a particular input sequence to the IC being tested (the device under testing), and detecting a change in the output sequence, because the output sequence will be different when there is a fault and when there is not a fault. The input sequence used for testing is known as the test sequence. One measure used for evaluating test sequence generation (test generation) is fault coverage of fault efficiency, which is defined as:
DF+UDF/F
Wherein DF represents the number of detected faults, UDF represents the number of undetectable faults and F represents the total number of faults.
Note that a fault coverage rating of 100% is referred to as total fault coverage.
Test generation algorithms for automatically generating test patterns (or test sequences) used for testing integrated circuit logic devices are known from the literature. Efficient test generation algorithms for combinational circuit test generation have also been proposed (see Fujiwara, H., “Logic Testing and Design for Testability,” The MIT Press, 1985).
It is also possible to achieve total fault coverage in a practical test generation time for combinational circuits. With sequential circuits, however, the number of states is 2
n
where n is the number of flip-flops. Test generation for sequential circuits therefore requires significant time, and it is generally difficult to achieve the total fault coverage.
To address this problem, full-scan design-for-testability and non-scan design-for-testability methods for automatically designing and modifying testable circuits have been proposed as design techniques for implementing controllers' and other sequential circuits in an integrated circuit.
The full-scan design-for-testability is described in, for example, the above-cited “Logic Testing and Design for Testability,” and is described briefly below with reference to FIG.
22
.
A controller or other sequential circuit comprises a state register
102
and combinational circuit
100
as shown in FIG.
22
. In full-scan design-for-testability, all flip-flops in the state register
102
are replaced by scannable flip-flops. The flip-flops are externally controllable and observable. More specifically, the state register
102
is replaced by a scannable register
103
having scan-in Si and scan-out SO contacts. During testing, this arrangement enables the state of the scannable state register
103
to be controlled to a desired state by controlling the scan-in SI contact, and enables the value resulting from that input to be observed using the scan-out SO contact. It is thus also possible to generate tests for combinational circuits
110
in which the scannable state register
103
is replaced by a pseudo-primary input PPI and a pseudo-primary output PPO as shown in FIG.
24
.
It is therefore possible to use a test generation algorithm for a combinational circuit, shorten the test generation time compared with the original sequential circuit (FIG.
22
), and achieve total fault coverage.
It will also be obvious, however, that the test sequence length increases when as the number of flip-flops in the state register increases. Each time the system clock advances, it is also necessary apply an input vector to the state register, and sequentially read and observe (scan-out) the content (scan-in) of the state register. The problem with full-scan design-for-testability, therefore, is that testing at the actual operating speed is not possible.
The non-scan design-for-testability method was proposed by Chickermane, et al., to address the problem of testing at the actual operating speed (see Chickermane, V., E. M. Rudnick, P. Banerjee, and J. H. Patel, “Non-Scan Design-for-Testability Techniques for Sequential Circuits,” ACM/ICEE 30th Design Automation Conference, pp. 236-241, 1993). As shown in
FIG. 25
, Chickermane et al. divide the one state register into two state registers, a first register
102
a
having only as many flip-flops as inputs thereto, and a second register
102
b
having the remaining flip-flops A multiplexer
122
is also added for improving testability by externally setting the value of the first register
102
a
during testing.
This non-scan design-for-testability method enables testing at the actual operating speed, but it is difficult to set all states of the state register to the desired states due to practical limitations on the number of primary input pins. The problem with this method is thus that test generation for sequential circuits is necessary, high fault coverage cannot be achieved, and the test sequence length becomes significant.
There is therefore a need for an integrated circuit and for an integrated circuit design method whereby increasing the length of the test sequence for controllers and other sequential circuits can be suppressed, high fault coverage can be achieved, and testing at the actual operating speed can be achieved.
SUMMARY OF THE INVENTION
To meet the above described need, an object of the present invention is to provide an integrated circuit having a sequential circuit describable as a finite state machine, comprising a state register and combinational circuit, and controllable to a reset state by inputting a reset signal thereto.
To this end, the integrated circuit comprises a mode selection means enabling selection of a specific state transition mode for effecting state transitions different from the state transitions of the finite state machine; an invalid-state generation logic circuit for changing to all selectable invalid states on a state transition path when a specific state transition mode is selected by the mode selection means, based on a process for generating a set of test patterns by applying a specific test generation algorithm to the combinational circuit on an assumption that state register states are controllable and observable, and determining a state transition path passing through all invalid states indicated by a test pattern part corresponding to a state register setting in each test pattern of a test pattern set, said invalid state being defined as any state expressible by the state register but not directly selectable from the reset state of the finite state machine; and a primary observation output for externally observing each signal input to the state register as a signal indicating a value to which the state register is to be set.
A further object of the invention is to provide a design-for-testability method for an integrated circuit having a sequential circuit describable as a finite state machine having a finite number of states, including a reset state.
To this end, the design-for-testability method comprises a logic circuit generating step for generating a logic circuit comprising a state register and a combinational circuit by logic synthesis of a finite state machine described at a register transfer level; a test pattern set generating step for generating a set of test patterns by applying a specific test generation algorithm to said combinational circuit using an assumption that state register states are controllable and observable; a transition-resistant valid state detection step for detecting as a transition-resistant valid state a valid states where the transition sequence required to select that state exceeds a predefined length, or the processing time required to determine a transition sequence for selecting that state exceeds a predefined limit, such valid state being defined as any state directly selectable by the finite state machine from a reset state thereof; a state transition path determining step for determining a state transition path pass
Fujiwara Hideo
Masuzawa Toshimitsu
Ohtake Satoshi
De'cady Albert
McDermott & Will & Emery
Semiconductor Technology Academic Research Center
Torres Joseph
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