Testable bus control logic circuitry and method for using same

Details Testable bus control logic circuitry and method for using same Testable bus control logic circuitry and method for using same

1998-08-31

2000-10-17

Tu, Christine Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Transmission facility testing

714730, 326 56, G11C 2900, G01R 3128

Patent

active

061346829

ABSTRACT:
A bus control logic circuit is provided that may be tested for a variety of bus fault conditions including no-connection faults, cross-connection faults and bus-contention stuck faults. The bus control logic circuit operates in a normal mode and in a test mode. In the normal mode, the bus control logic circuit operates as a conventional driver decoder and is testable for no-connection faults and cross-connection faults. In the test mode, the bus control logic circuit also is testable for bus-contention stuck faults. To test for bus-contention stuck faults, drivers having addresses of a first parity are hard disabled and one of the hard disabled drivers is addressed. Because the addressed driver is hard disabled, the only driver that can be enabled is a non-addressed driver erroneously enabled due to a bus-contention stuck fault. To detect the bus-contention stuck fault, the signal line is placed in a known logic state that only changes if a driver is erroneously enabled due to a bus-contention stuck fault. Therefore, a change in the logic state of the signal line indicates the presence of a bus-contention stuck fault.

REFERENCES:
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patent: 5999013 (1999-12-01), Elliott

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