Test vector compression method

Details Test vector compression method Test vector compression method

2001-03-09

2004-05-04

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S728000

Reexamination Certificate

active

06732312

ABSTRACT:

TECHNICAL FIELD
The invention relates to automatic test equipment for testing complex systems and integrated circuits. In particular, the invention relates to the generation and storage of test vectors used in automated test equipment.
BACKGROUND ART
Systems and the integrated circuits (ICs) or semiconductors that invariably make up the systems are continuing to evolve and become more and more complex. The complexity increases witnessed in the past and anticipated in the future have led to the extensive and widespread use of automated test equipment (ATE) for testing these systems and their constituent circuits. In fact, in some cases, system complexity has increased to such an extent that accurate and complete manual testing is either impractical or even impossible. In addition to making accurate and relatively complete testing practical in the case of complex systems, automated testing using is ATEs can and does significantly reduce the costs of producing a system and/or its constituent parts. A trend toward using ATEs for testing even simple systems and ICs has been evident for some time. Today it is fair to say that virtually all major systems and IC manufacturing lines use some form of ATE.
As illustrated as a block diagram in
FIG. 1A
, a typical ATE
10
comprises a central processing unit (CPU)
14
, memory
12
, input/output (I/O)
16
hardware, and usually some form of operator interface
18
. The CPU
14
controls the operation of the ATE
10
employing a test vector stored in memory
12
. The test vector, often produced by an external source
20
, is transmitted to the ATE and loaded into memory
12
using the I/O hardware
16
. During the automated test, the CPU
14
reads the test vector from memory and controls the I/O hardware
16
in order to affect a test of the device under test (DUT)
30
. The operator interacts with the ATE through the operator interface
18
. For simplicity, the system or IC being tested will be referred to hereinbelow as the DUT.
As noted hereinabove, a typical automated test by an ATE employs a test vector. A test vector is a sequence of test operations to be performed and/or test values to be applied by the ATE to the system or IC under test. In most modern ATEs, the test vector is a binary sequence owing to the overwhelming use of digital computers and memory in ATEs and the propensity for complex systems to be largely digital. Each test vector used by the ATE is normally generated by first consulting a design database or specification that identifies the functionality of the system or IC being tested. A test vector for a given DUT is generated by ‘mapping’ or translating the desired DUT functionality testing into the functionality testing capability of the ATE. The test vector is then typically transmitted to the ATE and stored in the ATE memory. The test vector subsequently controls the test of the DUT by the ATE.
FIG. 1B
illustrates a flow chart of the steps in the conventional method of performing an automated test of a DUT using an ATE
10
. The method of automated testing comprises the step of consulting
40
design specifications. The design specification defines the performance of the DUT and helps determine the tests that should be performed during automated testing. The method of automated testing further comprises the step of generating
42
a test vector. Typically the step of generating a test vector employs an apparatus or computer program called an automated test pattern generator (ATPG) that utilizes information from the design specification to generate test vectors that adequately test the DUT. In the conventional method of automated testing, the step of generating a test vector
42
is followed by a step of creating
44
a completely specified test vector. The test vector generated by the step of generating
42
typically has a number, often a large number, of so-called ‘don't care’ states. The step of creating
44
a completely specified test vector assigns explicit values to the ‘don't care’ states in the test vector. Often this assignment is accomplished by using a random sequence generated by a step of generating
43
a random sequence.
The step of creating
44
the completely specified test vector of the conventional method of automated testing is sometimes followed by an optional step of compressing
46
the completely specified test vector to reduce the size of the test vector. The method of automated testing further comprises the step of transmitting and storing
48
the completely specified and possibly compressed test vector in the memory
12
of the ATE
10
. The ATE
10
utilizes the stored completely specified test vector in the step of testing
52
to complete the method of automated testing. If the completely specified test vector has been compressed, it must be decompressed in a step of decompressing
50
the completely specified test vector. The optional steps of compressing
46
and decompressing
50
are illustrated by dashed-line boxes in FIG.
1
B.
As mentioned above, the test vector is a binary sequence. Much of following discussion assumes that the testing of digital devices with a binary test vector is without loss of generality. One skilled in the art could easily extend the concepts expressed hereinbelow to a digital test situation. The testing functionality of the ATE normally exceeds required functionality testing for a given DUT. In addition, not all possible combinations of inputs and outputs need to be tested in a typical DUT to verify that it is operational and/or to locate faults. The result is that the test vectors invariably contain a large number of unspecified or ‘don't care’ states in addition to specified states (i.e. those having explicitly specified values). In most situations, there are many more ‘don't care’ states in a given test vector than there are specified states.
As used herein, a specified state is an element of the test vector that is assigned a specific value as a result of mapping the DUT test functionality into ATE test functionality. A ‘don't care’ state is an element in the test vector that is not specified by the DUT to ATE functionality mapping and so, can take on any value constrained only by the limits placed on an element in the test vector. For example, in the case of a binary test vector, the specified state is either a ‘1’ or a ‘0’, as specified by the mapping. The ‘don't care’ state can be either a ‘1’ or a ‘0’ and is not specified by the mapping.
As discussed hereinabove, the test vector is usually constructed or generated using an apparatus or computer program known as an ATPG. For a digital case, the ATPG typically generates the test vector based on the DUT test specification using three-level logic consisting of {1, 0, X} where the X is a ‘don't care’ value indicating a ‘don't care’ state. Thus, the test vector is initially filled with a sequence of ‘1’s, ‘0’s and ‘X’s. The method defining how the ATPG decides to construct a test vector is beyond the scope of this discussion. In general, however, the ATPG generally attempts to construct a test vector that maximizes the probability of finding all potential faults while simultaneously minimizing the test time for a given DUT.
The test vector, when transmitted to and stored in the ATE memory, must have an unambiguous value. Therefore, the ATPG must assign a deterministic value to all ‘don't care’ states. Typically the assignment of a value to a ‘don't care’ state by the ATPG is accomplished using a random sequence generator. The random sequence generator “fills” the ‘don't care’ states of the test vector with random values. For example, in the case of a binary test vector, the specified states are assigned the appropriate value, either ‘1’ or ‘0’ and then a random sequence generator that generates a random binary string is consulted to fill the ‘don't care’ states.
FIG. 2
illustrates an example of a typical test vector, as generated by the produce a conventional, completely specified test vector. In the first line
81
of
FIG. 2

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