Test vector generating method and test vector generating...

Details Test vector generating method and test vector generating... Test vector generating method and test vector generating...

2006-07-12

2010-06-22

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S728000

Reexamination Certificate

active

07743306

ABSTRACT:
The X-type of each bit permutation is determined (step301). When there are X-types except for X-type1, i.e., X-type with no don't-care bits, total capture state transition numbers TECTA1and TECTA2for capture clock pulses C1and C2are calculated (step303). As a result, when TECTA1>TECTA2, an X-type is selected for the capture clock pulse C1and a first X-filling processing is performed (see step305). On the other hand, when TECTA1≦TECTA2, an X-type is selected for the capture clock pulse C2and a second X-filling processing is performed (step306).

REFERENCES:
patent: 5305328 (1994-04-01), Motohara et al.
patent: 5418792 (1995-05-01), Maamari
patent: 5590135 (1996-12-01), Abramovici et al.
patent: 5625630 (1997-04-01), Abramovici et al.
patent: 5737341 (1998-04-01), Hosokawa
patent: 6327687 (2001-12-01), Rajski et al.
patent: 6543020 (2003-04-01), Rajski et al.
patent: 6728917 (2004-04-01), Abramovici et al.
patent: 6751767 (2004-06-01), Toumiya
patent: 6795948 (2004-09-01), Lin et al.
patent: 6836856 (2004-12-01), Blanton
patent: 6865706 (2005-03-01), Rohrbaugh et al.
patent: 7000202 (2006-02-01), Srinivasan et al.
patent: 7124342 (2006-10-01), Wang et al.
patent: 2004/0250186 (2004-12-01), Takasaki
patent: 4-244979 (1992-09-01), None
patent: 2001-99901 (2001-04-01), None
patent: 2004-361351 (2004-12-01), None
M. Abramovici, M. Breuer, and A. Friedman, “Digital Systems Testing and Testable Design”, Computer Science Press, 1990.
X. Lin, J. Rajski, I. Pomeranz, S. M. Reddy, “On Static Test Compaction and Test Pattern Ordering for Scan Designs”, Proc. Intl. Test Conf., pp. 1088-1097, 2001.
S. Kajihara, K. Ishida, and K. Miyase, “Test Vector Modification for Power Reduction during Scan Testing”, Proc. VLSI Test Symp., pp. 160-165, 2002.
X. Wen, Y. Yamashita, S. Kajihara, L. Wang, K. K. Saluja, and K. Kinoshita, “On Low-Caputre-Power Test Generation for Scan Testing”, Proc. VLSI Test Symp., pp. 265-270, 2005.
R. Sankaralingam, R. Oruganti, and N. Touba, “Static Compaction Techniques to Control Scan Vector Power Dissipation”, Proc. VLSI Test Symp., pp. 35-40, 2000.
PCT/IB/326, Feb. 2008.
PCT/IB/338, Feb. 2008.
PCT/IB/373, Jan. 2008.
PCT/ISA/237, Oct. 2006.
English-Language translation of PCT/ISA/237, Oct. 2006.

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