Tester arrangement comprising a connection module for testing, b

Details Tester arrangement comprising a connection module for testing, b Tester arrangement comprising a connection module for testing, b

1994-05-26

1999-11-02

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714733, G01R 3138

Patent

active

059789450

ABSTRACT:
The invention relates to an arrangement for testing, by way of the Boundary Scan Test method, carriers on which there are provided a number of ICs with BST logic and a number of ICs without BST logic. The arrangement comprises a connection module enabling the testing of such carriers also when the ICs without BST logic are fast in comparison with the neighboring BST logic.

REFERENCES:
patent: 5331274 (1994-07-01), Jarwala et al.
patent: 5377199 (1994-12-01), Fandrich
patent: 5404358 (1995-04-01), Russell
patent: 5428624 (1995-06-01), Blair et al.
Bleeker, "Pumping out the vectors", Test Magazine, Sep. 1993, pp. 9-10.
"Boundary-Scan Test--A Practical Approach", by H. Bleeker et al, Kluwer 1993, pp. 157,166.

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