Testability architecture for modularized integrated circuits

Details Testability architecture for modularized integrated circuits Testability architecture for modularized integrated circuits

1999-11-02

2002-12-10

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C370S242000

Reexamination Certificate

active

06493840

ABSTRACT:

BACKGROUND
1. Field of the Invention
This invention relates to testing of integrated circuits, and to on-chip circuitry for supporting testing of modularized (“loosely integrated”) integrated circuits.
2. Background
There are types of chips (integrated circuits), e.g. PC87306, PC87307 or PC87317, where each chip includes several circuit modules that are independent of each other (“loosely integrated”); these modules have no direct interface with one another. Each independent module receives its input signals either from a central configuration module (CFG) or directly from the I/O (input/output) (terminals) pins of the chip. In a similar way, each module's output signals are connected either to the CFG or to the I/O. There is also a clock module whose interface is treated as I/O controlled by the CFG. An example of a module is a block of logic circuitry for performing a particular function; a module can include logic and/or memory.
FIG. 1
shows such a chip
10
with modules
1
,
2
,
3
, and
4
and CFG
12
, having I/O connections
16
to I/O
18
. Each module is provided with I/O connections
20
,
22
,
24
,
26
, and connections
30
,
32
,
34
,
36
to the CFG. The CFG
12
also provides I/O control signals for the direction of the I/O, multiplexed functions on one chip pin, etc.
In the prior development (design) process for such chips, one module design is used in various otherwise different chips. However the modules' test vectors (test signals used for testing the chip during production) must be regenerated for each new chip. As a result, the process of generating correct test vectors and testing a new chip is expensive and time consuming.
The main reasons for changing test vectors for a module design used in several different chips are:
1. Changes in the CFG module from chip to chip.
2. Changes in the I/O from chip to chip; these changes require that a particular module design will be connected to different I/O pins in different chips.
Changes in the test vectors necessitate new fault-grading to ensure adequate coverage of the new test program. This lengthy process is seldom done, and the resulting inadequate test coverage results in chip failures.
Since test vectors cannot be used “as is” for new chips, this delays commercial production of the chip, incurs additional cost for the test program development, and causes poor fault coverage of the test program, resulting in chip failures.
SUMMARY
This prior art testing problem is addressed by adding circuits to the CFG and to the I/O portions of a chip, and providing a method to test each module design using these additional circuits, as a “stand alone module” regardless of the actual chip in which that module design is used. Therefore in the test mode, each module design is exposed to the same test pattern, regardless of the chip into which it is integrated. This allows easy integration of the module design in new chips, regardless of the chip CFG module and the I/O pin assignment, and chip area is enlarged only slightly (e.g. 1% or less). Hence there is no need to generate new test vectors and change test programs for an existing “stand alone module”. Therefore once a module design has reached an adequate level of fault coverage, there is no need to repeat the test design process for each new chip, because the old test vectors are used.


REFERENCES:
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patent: 5432441 (1995-07-01), El-Ayat et al.
patent: 5517515 (1996-05-01), Spall et al.
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patent: 6272656 (2001-08-01), Yoshiyama
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