Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-04-28
2001-11-20
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C714S727000
Reexamination Certificate
active
06321354
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronic devices having a low number of leads with predefined functions, and especially portable electronic devices of the “SMARTCARD” type. The present invention more specifically relates to the testing of such electronic devices.
2. Discussion of the Related Art
FIG. 1
schematically shows the internal structure of an electronic device
10
of the “SMARTCARD” type. The device includes a microcontroller
12
, or core, coupled to a peripheral
14
by a conventional bus including data lines D, address lines A, and control lines C. Further, microcontroller
12
receives interruptions INT from peripheral
14
.
The device only includes eight leads having very precise functions. Two leads, Vdd and Vss, are used to supply the device. An input/output lead I/O forms the only input path to microcontroller
12
. Peripheral
14
is connected to a data input lead Din and to a data output lead Dout. The microcontroller is clocked via a clock lead CLK while peripheral
14
is clocked independently via a clock lead DCLK. A general reset lead RST is used to reset all elements of device
10
.
The devices of the type of
FIG. 1
are often used to decrypt data. In this case, the encrypted data arrive on lead Din, undergo processing in peripheral
14
determined by microcontroller
12
, and come out decrypted through lead Dout. The data are processed asynchronously with respect to the operation of the microcontroller, which explains the use of two clocks CLK and DCLK. The key used for the decryption, which thus determines the processings to be performed by peripheral
14
, is stored inaccessibly in microcontroller
12
. Thus, for security reasons, the possibilities of action upon microcontroller
12
via lead I/O are limited.
Lead I/O especially enables setting microcontroller
12
in a test mode to perform an exhaustive test of the microcontroller. Lead I/O then is by default in the input mode.
The several actions authorized from the outside on microcontroller
12
are obtained by exchanging information through lead I/O according to a predefined protocol.
A disadvantage of such a device is that its possibilities, especially for testing, are particularly limited due to the low number of leads all having assigned functions and due to the fact that the possibilities of access to the device via lead I/O are limited for security reasons.
Further, microcontroller
12
being programmed to interpret the protocol, perform the required actions, and return the results via lead I/O, the actions must remain simple in order not to increase the memory capacity of the microcontroller and thus the size of the device. The programming no longer allows the protocol to vary.
Finally, this device is poorly adapted to the testing of complex peripherals, since the tests performed, as they are extremely varied, are difficult to codify with a protocol. The information to be sent back to the microcontroller through data lines D or interrupt lines INT can only be established after the execution of complex sequences which are difficult to integrate to the protocol.
SUMMARY OF THE INVENTION
An object of the present invention is to render a large number of elements of a device of the above-mentioned type testable from the outside.
This and other objects are achieved by means of an electronic device including a microcontroller which can be set in a specific mode in which internal registers can be modified from outside; a peripheral internally coupled to the microcontroller via interface registers; a single input/output lead for communicating with the microcontroller from the outside; a peripheral input lead and a peripheral output lead; a microcontroller clock lead and a peripheral clock lead. The interface registers can be connected according to a shift register configuration forming a test scan path accessible in series and clocked by a clock signal to be applied to the peripheral clock lead. A test aid circuit, in a scan mode, connects the interface registers according to the shift register configuration, the scan mode being selected when a test bit, accessible through the input/output lead, is enabled , and when the input/output lead is forced from the outside to a state distinct from its default state.
According to an embodiment of the present invention, the device further includes a general reset lead directly connected to a reset input of the microcontroller. This general reset lead is connected to a reset input of the peripheral via a flip-flop connected in the scan path.
According to an embodiment of the present invention, the content of the flip-flop can be modified by the microcontroller.
According to an embodiment of the present invention, the peripheral includes a memory which the microcontroller accesses in the read mode through an internal bus. A flip-flop is connected in the scan path, an active state of which causes a reading from said memory, a capture register, also connected in the scan path, being provided for storing the word presented at the memory output.
According to an embodiment of the present invention, the device includes means for preventing the activation of the reset of the peripheral by a state of the flip-flop when the scan mode is selected.
The present invention also provides a method of testing a device of the above-mentioned type, including the steps of enabling the test bit via the input/output lead; stopping the clock of the microcontroller; forcing the input/output lead to the state opposite to its default state; and inputting or extracting data in series at the rate of the peripheral clock in the scan path through the input lead or through the output lead of the peripheral.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
REFERENCES:
patent: 4623888 (1986-11-01), Waring
patent: 4995039 (1991-02-01), Sakashita et al.
patent: 5157781 (1992-10-01), Harwood et al.
patent: 5561761 (1996-10-01), Hicok et al.
patent: 5590354 (1996-12-01), Klapproth et al.
patent: 5617531 (1997-04-01), Crouch et al.
patent: 5784382 (1998-07-01), Byers et al.
patent: 5898701 (1999-04-01), Johnson
patent: 5936977 (1999-08-01), Churchill et al.
patent: 5953285 (1999-09-01), Churchill et al.
patent: 5968114 (1999-10-01), Wentka et al.
French Search Report from French Patent Application 97 05592, filed Apr. 29, 1997.
SGS-Thomson Microelectronics S.A.
Ton David
LandOfFree
Testable circuit with a low number of leads does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Testable circuit with a low number of leads, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Testable circuit with a low number of leads will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2596579