Testable design methodology for clock domain crossing

Details Testable design methodology for clock domain crossing Testable design methodology for clock domain crossing

2007-11-06

2007-11-06

Tu, Christine T. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S798000, C375S354000

Reexamination Certificate

active

11294761

ABSTRACT:
A design methodology to debug synchronization of a signal crossing clock domains. A testable synchronization control logic utilizes a programmable register to set parameters to test signals traversing from one clock domain to another clock domain across a synchronization circuit. The register is programmed with a latency value that corresponds to a correct synchronization timing for the clock domain crossing. Other bit entries in the register provide setting of other debug parameters and indications of monitored results.

REFERENCES:
patent: 5987081 (1999-11-01), Csoppenszky et al.
patent: 6260152 (2001-07-01), Cole et al.
patent: 2007/0008758 (2007-01-01), Waldrop

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