Testable up down counter for use in a logic analyzer

Details Testable up down counter for use in a logic analyzer Testable up down counter for use in a logic analyzer

2005-05-17

2005-05-17

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

C714S724000, C714S033000, C714S039000

Reexamination Certificate

active

06895536

ABSTRACT:
A logic analyzer according to the subject invention employs a bi-directional counter that can be incremented in response to detection of certain events, and decremented in response to detection of other, different, events. Both an overflow (incremented to a predetermined count) and an underflow (decremented to a predetermined count) can be tested by a trigger machine of the Logic Analyzer.

REFERENCES:
patent: 6128754 (2000-10-01), Graeve et al.
patent: 6377065 (2002-04-01), Le et al.
patent: 6526501 (2003-02-01), Edwards et al.

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