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Chip leads constrained in dielectric media

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate

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Chip mounting plate construction of lead frame for semiconductor

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Patent

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Chip mounting scheme

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With heat sink means
Patent

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Chip on board assembly without wire bonding

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Patent

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Chip on board with heat sink attachment

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With heat sink means
Reexamination Certificate

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Chip on lead frame for small package speed sensor

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate

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Chip package

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With heat sink means
Patent

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Chip package and electrical connection structure between...

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate

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Chip package enabling increased input/output density

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With dam or vent for encapsulant
Reexamination Certificate

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Chip package having asymmetric molding

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With dam or vent for encapsulant
Reexamination Certificate

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Chip package having with asymmetric molding and turbulent...

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With stress relief
Reexamination Certificate

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Chip package structure and fabricating method thereof

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With bumps on ends of lead fingers to connect to semiconductor
Reexamination Certificate

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Chip package structure and manufacturing method thereof

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With heat sink means
Reexamination Certificate

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Chip package with a dam structure on a die pad

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate

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Chip package with asymmetric molding

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate

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Chip packages with covers

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate

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Chip packaging

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate

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Chip scale package

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate

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Chip scale package having flip chip interconnect on die paddle

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With bumps on ends of lead fingers to connect to semiconductor
Reexamination Certificate

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Chip scale package of semiconductor

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate

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