Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With bumps on ends of lead fingers to connect to semiconductor
Reexamination Certificate
2005-11-15
2011-11-29
Chu, Chris (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With bumps on ends of lead fingers to connect to semiconductor
C257SE21519, C257S666000, C438S123000
Reexamination Certificate
active
08067823
ABSTRACT:
A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has interconnection between the active site of the die and the die paddle. Also, methods for making the package are disclosed.
REFERENCES:
patent: 4005472 (1977-01-01), Harris et al.
patent: 4122215 (1978-10-01), Vratny
patent: 4707724 (1987-11-01), Suzuki et al.
patent: 5414299 (1995-05-01), Wang et al.
patent: 5811877 (1998-09-01), Miyano et al.
patent: 6028011 (2000-02-01), Takase et al.
patent: 6083645 (2000-07-01), Takeuchi
patent: 6593545 (2003-07-01), Greenwood et al.
patent: 6597059 (2003-07-01), McCann et al.
patent: 6927478 (2005-08-01), Paek
patent: 6953988 (2005-10-01), Seo et al.
patent: 7045882 (2006-05-01), Paek
patent: 7045883 (2006-05-01), McCann et al.
patent: 7064009 (2006-06-01), McCann et al.
patent: 7112871 (2006-09-01), Shiu et al.
patent: 2002/0020907 (2002-02-01), Seo et al.
patent: 2003/0001252 (2003-01-01), Ku et al.
patent: 2006/0214308 (2006-09-01), Yu et al.
Atkins Robert D.
Chu Chris
Patent Law Group
STATS ChipPAC Ltd.
LandOfFree
Chip scale package having flip chip interconnect on die paddle does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Chip scale package having flip chip interconnect on die paddle, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chip scale package having flip chip interconnect on die paddle will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4259137