Chip scale package

Details Chip scale package Chip scale package

1999-12-07

2001-10-02

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S676000

Reexamination Certificate

active

06297543

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a chip scale package, more particularly to a chip scale package having a plurality of solder balls as external connection terminals mounted on a substrate.
2. Description of the Related Art
As for examples of package, there have been used various packages, i.e. SOJ(small outline J-lead) type for general use, ZIP (zigzag inline package) type for particular use, and TSOP (thin small outline package) type having a construction suitable for memory cards which have been standardized gradually.
Method for manufacturing those packages may be summarized as follows.
At first, a wafer is separated into individual semiconductor chips by performing a sawing process for cutting the wafer along a scribing line, and a die-attaching process is performed for attaching inner leads of lead frames to the respective semiconductor chips.
A resultant is cured thereafter, a wire-bonding process is performed for electrically connecting bonding pads of the semiconductor chips and the inner leads of the lead frames.
After the wire-bonding process, an encapsulating process for encapsulating the semiconductor chips with molding compound. By encapsulating the semiconductor chips as above, the semiconductor chips can be protected from external thermal or mechanical impacts.
After the encapsulating process as described above is completed, following are a plating process for plating outer leads; a trimming process for sawing a dam bar supporting the outer leads; and a forming process for bending the outer Leads by a selected figure so that the outer leads are easy to mount on a substrate.
In regard to the general packages as manufactured according to above steps, a chip scale package for lightening the package has a structure in which a plurality of solder balls are arranged in an array manner and the solder balls are mounted on the substrate.
FIG. 1
illustrates a package as disclosed in Japanese Patent Laid-open No. 8-125066. As disclosed, a lead frame
2
is attached to a bottom face of a semiconductor chip
1
by means of an adhesive
3
, and an inner lead
21
of the lead frame
2
is electrically connected to a bonding pad of the semiconductor chip
1
and the entire resultant is encapsulated with molding compound
4
such that an outer lead
22
of the lead frame
2
is exposed from the molding compound
4
. A solder ball
5
is mounted on the outer lead
22
exposed from the molding compound
4
.
However, in
FIG. 1
, the lead frame
2
makes “┐” figure, and its left end becomes the inner lead
21
and its lower right end becomes the outer lead
22
. Originally the figure was not the same figure as above, the figure was formed by partially etching a cross-section of bottom portion of a rectangular. Namely, thickness of the outer lead
22
is the original thickness of the lead frame
2
.
As the semiconductor chips are highly integrated and have a number of pins, the pitch between the inner leads
21
becomes fine. When the inner leads
21
are formed by partially etching with chemicals as in the conventional methods, thickness of the inner leads
21
is not uniform and etching face thereof is not even, especially corners often have curvaceous figures. If the inner leads of the lead frame have the foregoing figure, poor connection property is found during the wire-bonding process.
Further, during the wire-bonding process, it is required to adjust the metal wire
6
not being exposed below the molding compound
4
. However, it is very difficult to control bonding height since etching depth of the lead frame is not always uniform. In other words, there is a problem that the height should be controlled all the time precisely.
SUMMARY OF THE INVENTION
Accordingly, the present invention is provided to solve foregoing problems caused by the conventional packages. It is one object of the present invention to make the thickness of the inner leads to be equal to the original lead frames and to minimize the partial etching area thereby preventing the poor connection property during metal wire-bonding process.
The other object of the present invention is to make the process of adjusting the bonding height a lot easier by preventing the metal wire to be exposed from the molding compound.
To accomplish those objects of the present invention, the chip scale package according to the present invention is constructed as follows.
A lead frame is attached with an adhesive to a bottom face of a semiconductor chip in which a bonding pad is formed. An inner lead of the lead frame is connected to the bonding pad of the semiconductor chip with a metal wire, and thickness of the inner lead is equal to the original thickness of the lead frame. An outer lead of the lead frame is formed by partially etching a bottom face of the lead frame. The entire resultant is encapsulated with a molding compound such that the outer lead is exposed therefrom, especially there is formed a downward protruding portion at the molding compound below the inner lead. This protruding portion raises the margin of controlling the bonding height during the wire-bonding process such that the metal wire is not exposed from the molding compound. Furthermore, the outer leads at both sides where no solder balls are mounted on, are exposed from the molding compound. The outer leads at both sides being exposed from the molding compound act for dissipating outwardly heat that is transmitted from the semiconductor chip to the lead frame. A solder ball is mounted at inside of the outer leads exposed from the molding compound.
According to he foregoing construction, transformation in the lead frame can be prevented since the inner lead is not partially etched but is maintained the original thickness of the lead frame, and instead the outer lead is partially etched. Accordingly, poor quality in the wire-bonding can be prevented.


REFERENCES:
patent: 5677566 (1997-10-01), King et al.
patent: 5703407 (1997-12-01), Hori
patent: 6060768 (2000-05-01), Hayashida et al.
patent: 6075284 (2000-06-01), Choi et al.
patent: 6146918 (2000-11-01), Lee
patent: 08125066 (1996-05-01), None
patent: 08116015 (1996-05-01), None
patent: 09008207 (1997-01-01), None
patent: 09045818 (1997-02-01), None
patent: 09246427 (1997-09-01), None

Affiliated with

Also associated with

Rating

Chip scale package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Chip scale package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chip scale package will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2594734