Chip package enabling increased input/output density

Details Chip package enabling increased input/output density Chip package enabling increased input/output density

2001-09-28

2003-09-30

Elms, Richard (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With dam or vent for encapsulant

C257S672000, C257S675000, C257S706000

Reexamination Certificate

active

06627978

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an integrated chip package. More specifically, the present invention relates to an integrated chip package that increases input/output for a chip by using electrically conductive microvias on a backside of a die to connect to a superstrate.
BACKGROUND INFORMATION
Integrated circuits are installed in various types of packages in order to provide: external electrical connections for the transistors of the integrated circuit via a lead system; physical and environmental protection for the chip; and heat dissipation from the transistor. Rapid advances in integrated circuit technology have created pressure to push the limits on packaging technology. The number of transistors on a die (wafer) has been increasing exponentially for many years, and the size of these transistors has been decreasing dramatically as well. The problem arises of increasing the input/output from the integrated circuit in the die to a motherboard or other external hardware.
While designers can put millions of transistors on a die, they are greatly constrained by the limited input/output density that today's packaging technology can accommodate. There are limits to extending the envelope in some packaging attributes such as interconnect pitch (i.e., the distance between connections, e.g., the distance between solder bumps), materials, etc., from a reliability and manufacturing point of view. For example, the smallest interconnect pitch and dimensions available today are state of the art, and anything smaller to increase input/output density is either not reliable or poses significant manufacturing problems.
One method for increasing input/output from a chip that has been pursued in industry is the use of three-dimensional stacked die technology. However, this solution is primarily intended for low-heat dissipating devices such as Flash, SRAM, etc., since the package structure often does not allow for an adequate heat dissipation device (e.g., a heat sink). Such solutions are therefore inappropriate for microprocessors and various chipsets. Designers for microprocessors and various chipsets are forced to constrain input/output count at the cost of desired beneficial features in the chip.
Vias connecting the integrated circuit to a frontside of the wafer are constructed by etching, layering, masking, and other photo-lithographic techniques. However, the density of these frontside connections, or pads, is limited. The pitch, the distance between adjacent pads, is limited by current bonding technology, and therefore input/output from a frontside of the wafer is limited. Conductive micovias are sometimes used in substrates to make electrical connections to the die. These microvias connect the integrated circuit to an external connection which connects to a motherboard. This external connection may be by a ball grate array, a pin grid array, or any other method of electrical coupling available.
There is a need for increased input/output density with good heat dissipation for use with microprocessors, chipsets, etc. (e.g., any processor requiring high input/output count and good heat dissipation).


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