Chip package with asymmetric molding

Details Chip package with asymmetric molding Chip package with asymmetric molding

2011-06-21

2011-06-21

Doan, Theresa T (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S670000, C257S676000, C438S123000

Reexamination Certificate

active

07964940

ABSTRACT:
A chip package with asymmetric molding including a lead frame, a chip, an adhesive layer, bonding wires and an encapsulant, is provided. The lead frame includes a frame body and at least a turbulent plate. The frame body has inner lead portions and outer lead portions. The turbulent plate is bended upwards to form a bulge portion and the first end of the turbulent plate is connected to the frame body. The chip is fixed under the inner lead portions and the turbulent plate is located at one side of the chip. The adhesive layer is disposed between the chip and the inner lead portions, and the bonding wires are electrically connected between the chip and the corresponding inner lead portions, respectively. The encapsulant encapsulates at least the chip, the bonding wires, the inner lead portions, the adhesive layer and the turbulent plate.

REFERENCES:
patent: 6046504 (2000-04-01), Kimura
patent: 6122822 (2000-09-01), Liao
patent: 6414379 (2002-07-01), Chang et al.
patent: 7576416 (2009-08-01), Tu et al.
patent: 1355562 (2002-06-01), None
Chinese First Examination Report of China Application No. 2005100901070, dated on Oct. 12, 2007.

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