Chip package and electrical connection structure between...

Details Chip package and electrical connection structure between... Chip package and electrical connection structure between...

2006-10-31

2006-10-31

Tran, Mai-Huong (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257SE21504, C257SE23049, 43

Reexamination Certificate

active

07129568

ABSTRACT:
A chip package has lead frame, chip, generic wires, at least one characterized wire, ground wires and insulation material. The lead frame includes die pad, generic leads and at least a characterized lead structure. Generic leads and the characterized lead structure are aligned at peripheral region of the die pad. The characterized lead structure has a cross-sectional area perpendicular to the direction where signals transmit, which is larger than each generic lead. The chip is on the die pad. The generic wires connect the chip to the generic leads. The characterized wire connects the chip to the characterized lead structure. The characterized wire is for transmitting an identical signal between the chip and the characterized lead structure. Ground wires connect the chip to the die pad, and are located at both sides of the characterized wires. The insulation material encapsulates lead frame, chip, generic wires, characterized wire and ground wires.

REFERENCES:
patent: 5382546 (1995-01-01), Yamada et al.

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