Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
1997-10-09
2001-01-09
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S048000, C257S674000, C257S676000, C257S672000, C257S671000, C257S692000
Reexamination Certificate
active
06172413
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to packaging and testing of microchips. More particularly, the present invention relates to methods of packaging a microchip for testing prior to mounting the microchip upon a circuit board. Additionally, the present invention relates to methods of testing a packaged microchip that has a tight lead pitch. In particular, the present invention relates to a method of packaging and testing a microchip with a tight lead pitch, wherein the testing method uses a probe and allows for removal of that portion of the lead which made contact with the probe, thus providing a shorter lead length.
2. The Relevant Technology
Microelectronic devices, such as semiconductor devices, are usually packaged on a lead frame structure to permit interconnection with a larger system. Often, the lead frame structures are connected to a printed circuit board (PCB) which, in turn, is connected to a larger electronic system such as a computer or other device.
After fabrication of a semiconductor integrated circuit, the integrated circuit is put through a die sort procedure. Each individual die is electrically tested for electrical performance and proper circuit functioning. During a die sort procedure, the integrated circuit is mounted on a vacuum chuck and aligned to thin electrical probes that contact each of the bonding pads on the die. The probes are connected to power supplies that test the circuit and record the results. Dies which do not pass the die sort are eliminated from the processing line. Dies which pass the die sort are singulated as chips and packaged into semiconductor device packages. The packaged semiconductor devices may then be re-tested prior to a final test and shipment.
As high integration and higher processing speeds of semiconductor devices have been improved, miniaturization and increased reliability of electronic devices has also been pursued. Along with miniaturization of circuits, miniaturization of chip packages has been a goal. That is, improvements have been necessary for coping with the needs for miniaturization of the packages, for achieving higher processing speeds of the semiconductor devices, and for achieving multiple-pin devices with increasingly narrower pitches.
In such packaging technology of semiconductor devices, chip mounting has progressed from through-hole mounting on a PCB to surface mounting on one side of the PCB. For example, in packaging plastic, especially in order to improve the mounting density upon a PCB, there has been proposed a vertical surface mounted package (VSMP). In the VSMP, a package is mounted perpendicularly on a surface of a PCB and, thus, the surface mounting technology can be applied to the chip package.
With packaging miniaturization, there occur accompanying problems. One problem is that when a VSMP is to be mounted on a board, mounting has to be substantially precise. Substantially imprecise mounting can cause leads to be bent, misaligned, or can cause solder bridges to form therebetween. Any significantly improper board mounting leads to device failure.
Testing of chip packages with tight-pitch leads is problematic because testing probes may have a characteristic diameter, such as a width, that may be greater than the width of a lead plus the space on either side thereof. Although testing probes of smaller dimensions are manufacturable, they add a significant increase to costs. Additionally, testing probes often tend to damage the portion of a lead upon which the probe makes contact. When such damage occurs, the lead must be reformed, commonly called “spanking” the lead. Although lead spanking or other reforming operations can in many cases reshape the lead after testing, it is an additional processing step and yield can decrease.
Lead length is also an important part of the overall semiconductor device. A reduced lead length allows for such advantages as a lower inductance, a higher speed, and a lower capacitance and a smaller package. As lead dimensions continue to decrease in size, fabrication of a robust lead that stands up to necessary testing procedures becomes a greater challenge.
What is needed in the art is a method of testing a chip in a chip package that allows for lower cost including larger diameter testing probes that have a characteristic dimension that is greater than the lead width. What is also needed in the art is a reduced lead length in a chip package that is produced without the processing of lead spanking or similar reforming operations. What is also needed in the art is a method of testing a chip in a package wherein incidental damage of any kind to the contacted portion of the lead is inconsequential to the final chip package to be used in the field.
SUMMARY OF THE INVENTION
The present invention relates to a chip package and to methods of testing a chip package wherein contact is made by a configuration of testing leads in such a manner so as to allow for shorter and tighter-pitch leads than those used in the prior art or with contacts of the prior art that are robust, but that will not short out by contact with neighboring adjacent leads. The invention contemplated uses in a variety of chip packaging including ring pack, VSMP, zig-zag surface-mounted packages, and dual in-line surface-mounted packages.
During testing of a chip package, a testing device such as a test head with an array of pogo pins is used. In one embodiment of the chip package, an array of leads are provided. Upon at least one of the leads, a first contact location is found proximate to the chip package. Distal to the first contact location, a second contact location is found. Substantially at or near the lead terminal end, a third contact location is found. Where testing uses a contact such as a pogo pin, a contact cross-sectional footprint will be made upon the lead. The contact cross-sectional footprint has a characteristic dimension. The characteristic dimension may be greater than the width of the lead. The characteristic dimension is less than the sum of the width of the lead and twice the distance between a given lead and an immediate adjacent lead.
Where a lead pitch of 0.75 mm or smaller is to be used in a chip package, a conventional pogo pin will typically have a characteristic dimension such that staggering of the first contact location, the second contact location, and the third contact location, etc. allows for a more robust and less expensive pogo pin to be used without causing shorting of any given pogo pin by contact with an immediately adjacent pogo pin or bridging of a pogo pin between two adjacent occurrences of a lead.
In another embodiment, a contact cross-sectional footprint is imposed upon a lead at a first contact location and a second side contact cross-sectional footprint is imposed beneath a lead at a second contact location. In this embodiment, contact of the array of leads from altematingly opposite sides facilitates closer packing of the pogo pin with adjacent, same lead-side pogo pins by alternating pogo pins to make contact with a given lead from a first side and with the immediately adjacent lead from a second side. In another embodiment, a testing configuration features the contact cross-sectional footprint and second side contact cross-sectional footprint overlapping each other when viewed in plan view with the footprints depicted in cross-section.
An inventive structure of the present invention includes an array of leads, whereby the array of leads is constrained by a dielectric material. Because the array of leads is constrained in a dielectric material and is not shorted out into an electrically conductive material, testing of a chip package by making contact with the constrained leads with a probe such as a pogo pin can be carried out, whereby destructive bending of any lead is resisted by virtue of the constraining dielectric material.
A two-sided contact testing scheme is another embodiment according to the present invention wherein a pogo pin makes contact with a constrained lead from above a chip package, an
Clark Jhihan B
Micro)n Technology, Inc.
Saadat Mahshid
Workman & Nydegger & Seeley
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