Chip scale package of semiconductor

Details Chip scale package of semiconductor Chip scale package of semiconductor

2000-01-07

2001-01-23

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C438S123000

Reexamination Certificate

active

06177719

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88105092, filed Mar. 31, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a chip scale package (CSP), and more particularly to a chip scale package of semiconductor.
2. Description of Related Art
Following the development of the semiconductor industry, a lot of related new technology is continuously progressing and changing. The manufacturing process of a semiconductor product is generally divided into three stages, firstly the formation of semiconductor base, i.e. the portion of chip-forming technology; secondly, the manufacturing of semiconductor devices such as Metal Oxide Semiconductor (MOS.), the conductive wire inter-connection of stacked metal etc., lastly the packaging process. Today, almost all the efforts on the development of electronic products are heading for the target of light, thin, short. and small in dimension. For examples, these efforts are to raise the degree of intoglation for the semiconductor, and to provide various types of packaging technology such as Chip Scale Package (CSP), Multi-Chip Module (MCM) etc. As the manufacturing technology of semiconductor has progressed to such a tiny width as 0.18 &mgr;m of semiconductor elements, the degree of integration has become a great break through. Therefore, how to develop the corresponding tiny packages of semiconductor to achieve the object of minimizing the semiconductor products has become the important topic of study nowadays.
As far as the semiconductor devices of low-number-of-lead are concerned, for examples, high voltage transistor device and identification microchip etc., generally, lead frame is still employed as a chip carrier. Shown in
FIG. 1
is a schematic cross-sectional view of the semiconductor package of low-number-of-lead according to the prior art. Take a high voltage transistor device on the circuit board for example, the conventional high voltage transistor device is used for being functioned as a switch. This high voltage transistor device is a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) having three connecting points, a gate, a source, and a drain.
As shown in
FIG. 1
, the conventional chip scale package is a Small Outline Transistor (SOT) type with its lead frame possessing four leads
12
and a chip carrier
10
. After the chip
16
is bonded to the chip carrier
10
, by the use of wire bonding method, bond wire
18
is employed to connect the gate, source, and drain of the chip
16
to the lead
12
. Thereafter, a insulated material
20
is employed to encapsulate the chip
16
, the chip carrier
10
, the bond wire
18
, and the inner end of the lead
12
. The outer end of the lead
12
is to be formed as a Z-shaped lead (also called as a Gull-Wing type) to facilitate the follow-up SMT (Surface Mount Technique) fabrication.
The conventional chip scale package of the SOT type as described above is quite possible to increase the circuit impedance. Consequently, it will result in signal decay and signal delay since the input/output of the signal is unable to transmit to the chip
10
without passing through the path including the lead and the wire which is relatively lengthy. As far as the mass production type of semiconductor technology of today is concerned, for the MOSELT with 0.4 &mgr;m of lead width, the resistance as low as 0.2 mini-ohm-cm has been achieved. However, the resistance of the lead of the conventional chip scale package is as high as 20 mini-ohm-cm that is totally unmatched to the chip, and thereby seriously affecting the performance of the device. In additions, this type of packaging makes the volume of the device increase, the area of application is therefore limited, besides, it contradicts the design principle of light, thin, short, and small in dimension.
SUMMARY OF THE INVENTION
It is the first objective of the present invention to provide a chip scale package of semiconductor to shorten the signal-transmitting path in order to raise the chip performance.
It is the second objective of the present invention to provide a chip scale package of semiconductor to make use of the method of the “chip scale package” in order to diminish the volume of the package.
It is the third objective of the present invention to provide a chip scale package of semiconductor to simplify packaging process and to lower the cost of packaging.
It is the fourth objective of the present invention to provide a chip scale package of semiconductor to improve the thermal dissipation problem.
In order to attain the foregoing and other objectives, the present invention provides a ball grid array package that can be fabricated on a print circuit board. The chip scale package of semiconductor of the present invention comprises a chip having multiple electrodes, a plurality of conductive blocks, and an insulating material. The electrodes of the chip are electrically connected to the conductive blocks respectively through one of the surfaces thereof by a conductive bond, and are electrically connected to the circuit on the print circuit board through the side surfaces thereof. The insulated material is filled on the chip surface between the conductive blocks, and in the gap between the conductive blocks and the chip.
According to a preferred embodiment of the present invention, the foregoing electrodes can be disposed on either one surface or on both of the two surfaces. In additions, the bonding surface between the conductive block and the print circuit board preferably includes a plated layer to strengthen the bonding capability between them.
Moreover, in order to attain the foregoing and other objectives, a fabricating process of a chip scale package of semiconductor firstly provides a chip, having a first surface and a second surface. The first surface of the chip has a set-up of a gate and a first source/drain region, while the second surface of the chip has a set-up of a second source/drain region. Secondly, it provides a first conductive plate which is disposed on the first surface of the chip. T further comprises a substrate on which a first bump and a second bump are disposed on the same side. In this way, the first conductive plate can make the first bump and the gate as well as the second bump and the first source/drain region electrically couple respectively by using a conductive bond. Meanwhile, it provides a second conductive plate which is disposed on the second surface of the chip and is electrically coupled with the second source/drain region by a conductive bond. Thereafter, it fills an insulating material between the chip and the substrate as well as between the chip and the second conductive plate. Then, it removes the first conductive plate to expose a portion of the insulated substance which is disposed on the area excluding that covered by the first bump and the second bump on the first surface. Finally, it performs a sawing process to expose at least a side surface of the first bump, the second bump, the second conductive plate, and the chip to accomplish the foregoing chip scale package.
According to a preferred embodiment of the present invention, the foregoing process to remove a portion of the first conductive plate includes etching or sawing. The material of the conductive bond includes anisotropic conductive paste, anisotropic conductive film, solder film, conductive bump, or silver epoxy.
Since the electrodes of the chip depend only on the connection between the conductive block and print circuit board, and since the thickness of the conductive block of the present invention is only around 2-20 Mil (2-20×10
−3
inches), thereby, the signal transmitting path is significantly shorten. Consequently, the resistance can be lowered, and the problem of signal delay can be improved.
As the conductive block is sawed together with the chip, its area will be the same as that of the chip, and because the conductive block is rather thin in thickness, thereby, the overall packaging volume can be signifi

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