Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
1999-05-13
2001-02-06
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S676000, C257S723000, C257S777000, C257S786000
Reexamination Certificate
active
06184573
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a package including at least a semiconductor chip having at least a bump connected directly to a lead frame, and particularly to a dual-chip semiconductor package including at least two semiconductor chips each having at least a bump connected directly to a lead frame.
BACKGROUND OF THE INVENTION
With the use of wire-bonding or TAB (Tape Automated Bonding) technology, Conventional semiconductor packages, particularly the semiconductor packages each including at least two chips, suffer problems such as too long trace, connection of two lead frames, complicated material preparation and packaging processes, as well as the quality defects incurred in molding due to the weaker mechanical strength of TAB.
With semiconductor packages tending to be light and thin while chips gradually becomes larger in size to meet more sophisticated function demand, various schemes have been suggested for packaging a chip or more than a chip in such ways that the completed package as a whole can be smaller, particularly can be lighter and thinner. One among the various schemes is the prior art disclosed in U.S. Pat. No. 5,331,235 and represented by
FIG. 1
, which suggested a semiconductor package including at least two semiconductor chips
32
and
34
respectively having bumps
33
and
35
thereof facing each other and being connected to a lead frame
37
through tapes
31
, wherein a solder
36
is interposed between the two semiconductor chips; which also suggested another scheme as shown in
FIG. 2
where a semiconductor package C includes at least two semiconductor chips
32
and
34
respectively having bumps
33
and
35
thereof facing each other, and being connected to tapes
31
that are connected to lead frame
37
partly inserted between the two semiconductor chips
32
and
34
.
Although various schemes other than the above two were also suggested by the same prior art, they are all characterized by using tapes for electrical connection between bare chips and lead frames, thereby still suffer problems similar to those suffered by conventional semiconductor packaging, resulting in the need of developing a new scheme to keep pace with the trend of demanding renovated multi-chip semiconductor packages, leading to the suggestion of the present invention.
SUMMARY OF THE PRESENT INVENTION
Objects
It is a primary object of the invention to provide a semiconductor package including at least two chips having bumps thereon connected directly with a lead frame, in order to reduce manufacturing cost and completed package size, and to simplify packaging process as well as minimize production failure rate in packaging semiconductor chips.
It is another object of the invention to provide a method of packaging at least two semiconductor chips for reducing manufacturing cost and completed package size, and for simplifying packaging process as well as minimizing production failure rate.
It is a further object of the invention to provide a semiconductor package including at least a semiconductor chip and a lead frame wherein the lead frame is connected directly to the bump formed on the semiconductor chip so that the problems, particularly the inherent problem of long trace, suffered by prior arts can be minimized.
Introduction to the Invention
The semiconductor package suggested by the present invention is featured by the direct connection between the lead frame thereof and the bumps of the semiconductor chips therein, i.e., the semiconductor package according to the present invention is featured by comprising: at least two semiconductor chips each having at least a bump formed on the metal pad (such as Al pad) therein; and a lead frame having at least an inner lead connected with the bump on a first semiconductor chip of the two semiconductor chips and the bump on a second semiconductor chip of the two semiconductor chips, thereby there is no need of wire-bonding and TAB technology.
Obviously the above package may be enclosed by encapsulation through a molding process for convenient applications, as can be understood by anybody skilled in the art.
Although an embodiment of the above semiconductor package recommended by the present invention is such that the bump on the first semiconductor chip and the bump on the second semiconductor chip face each other and are connected directly with an inner lead of the lead frame, the semiconductor package according to the present invention is not limited to the configuration of connecting the inner lead to the two chips' respective bumps facing each other, instead, the scheme suggested by the present invention for connecting a lead frame directly to the bump of a chip may be applied to semiconductor packages of various configurations as long as the chip therein and the lead frame thereof are connected on the basis suggested by the present invention. It is therefore obvious that the present invention can be applied to a semiconductor package including a single chip.
The above semiconductor package may have its bump made of material selected from among solder, Au, Ni, and any substance providing electrical conductivity, and have its lead frame's inner lead in the width not larger than a size which approximately equals, before the inner lead is connected to the bump, the diameter of the bump; the lead frame is preferably made of material having wettability for connecting with solder in case the bump is a solder bump.
A method suggested by the present invention for packaging at least two semiconductor chips each having at least a bump thereon, and a lead frame having at least an inner lead, is characterized by comprising the steps of: connecting the inner lead to the bump on a first semiconductor chip of the two semiconductor chips; and connecting the bump on a second semiconductor chip of the two semiconductor chips with the inner lead, thereby a semiconductor packaging process can be facilitated and become relatively economical.
REFERENCES:
patent: 5349238 (1994-09-01), Ohsawa et al.
patent: 5677567 (1997-10-01), Ma et al.
patent: 5729440 (1998-03-01), Jimarez et al.
Bacon & Thomas
Potter Roy
Siliconware Precision Industries Co., LTD.
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