Chip package having with asymmetric molding and turbulent...

Details Chip package having with asymmetric molding and turbulent... Chip package having with asymmetric molding and turbulent...

2006-02-10

2009-08-18

Chu, Chris C (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With stress relief

C257SE23039, C257S666000, C257S667000, C257S676000

Reexamination Certificate

active

07576416

ABSTRACT:
A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.

REFERENCES:
patent: 4989068 (1991-01-01), Yasuhara et al.
patent: 5530286 (1996-06-01), Murakami et al.
patent: 6122822 (2000-09-01), Liao
patent: 6414379 (2002-07-01), Chang et al.
patent: 6576994 (2003-06-01), Iwaya et al.
patent: 2002/0109215 (2002-08-01), Iwaya et al.
patent: 2003/0062601 (2003-04-01), Harnden et al.

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