Read/write memory with improved test mode data compare

Details Read/write memory with improved test mode data compare Read/write memory with improved test mode data compare

1991-12-17

1994-02-08

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

371 211, G11C 2900

Patent

active

052854191

ABSTRACT:
An integrated circuit having a memory with a parallel test data comparator is disclosed. The parallel test data comparator includes a NOR-like function which has parallel transistors having their gates connected to an input from each of the internal data lines, and a NAND-like function which also has parallel transistors having their gates connected to an input from each of the internal data lines. The output nodes of each function are biased by single transistors, each controlled by a test enable signal, and each of which can be overpowered by any one of the parallel transistors. In the event that all of the internal data lines are at the same logic level, the outputs of the NOR and NAND will be at the same logic level; conversely, if any one (or more) of the internal data lines is different from the rest, the outputs of the NOR and NAND will be at different logic levels. An exclusive-OR-like function is used to generate a pass or fail signal responsive to the output nodes of the NOR and NAND.

REFERENCES:
patent: 4654849 (1987-03-01), White, Jr. et al.
patent: 4694274 (1987-09-01), Shimada
patent: 4860259 (1989-08-01), Tobita
patent: 5121358 (1992-06-01), Slemmer
McAdams, et al., "A 1-Mbit CMOS Dynamic RAM With Design-For-Test Functions", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5 (Oct. 1986), pp. 635-642.
Shimada et al., "A 46-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits vol. 23, No. 1 (Feb. 1988) pp. 53-58.

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