Random access memory with a simple test arrangement

Details Random access memory with a simple test arrangement Random access memory with a simple test arrangement

1996-03-01

1996-10-01

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Testing

365200, 36523003, G11C 700

Patent

active

055616364

ABSTRACT:
A quick test Input/Output (I/O) Random Access Memory (RAM). The RAM array may be divided into individual units. Each unit is further divided into subarray blocks (blocks of subarrays). Each subarray or segment is organized by one and includes one spare column and may include spare word lines. When a block is accessed, only half of the segments are accessed. Whenever a segment is accessed, the segment's spare column is not. Data from columns in the accessed half and spare columns in the unaccessed half are transferred to Local Data Lines (LDLs) and from LDLs to Master Data Lines (MDLs). Valid data from accessed column lines and from selected spare lines are provided on the MDLS to second sense amplifiers. Defective columns are electrically replaced with spares after the second stage amplifiers. During Compression Mode test, the complementary outputs of several Second Sense amplifiers are wire AND'ed to each other and EXOR'ed. The wire ANDed Second Sense Amps are then enabled, simultaneously. After Compression Mode test, if one of the complementary wire AND'ed outputs is high and the other is low, the EXOR output will be high indicating no error was detected. Otherwise, the RAM fails self-test.

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