Random access memory with rapid test pattern writing

Details Random access memory with rapid test pattern writing Random access memory with rapid test pattern writing

1991-10-16

1993-11-30

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

36523006, 371 213, G11C 1140

Patent

active

052672123

ABSTRACT:
A row address decoder generates row select signals and a column address decoder generates column select signals. A first group of logic gates combines the even-numbered column select signals with a first group select signal. A second group of logic gates combines the odd-numbered column select signals with a second group select signal. A third group of logic gates combines the even-numbered row select signals with a third group select signal. A fourth group of logic gates combines the odd-numbered row select signals with a fourth group select signal. Outputs of these logic gates select rows and columns in a memory cell array.

REFERENCES:
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patent: 4689772 (1987-08-01), Jordy et al.
patent: 4899307 (1990-02-01), Lenoski
patent: 4920515 (1990-04-01), Obata
patent: 5025422 (1991-06-01), Moriwaki et al.

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