Static information storage and retrieval – Read/write circuit – Testing
Patent
1998-12-11
2000-05-23
Hoang, Huan
Static information storage and retrieval
Read/write circuit
Testing
365200, 371 211, 371 225, G11C 700
Patent
active
060672625
ABSTRACT:
An efficient methodology for detecting and rejecting faulty integrated circuits with embedded memories utilizing stress factors during the manufacturing production testing process. In the disclosed embodiment of the invention, a stress factor is applied to an integrated circuit having built-in-self-test (BIST) circuitry and built-in-self-repair (BISR) circuitry. A BIST run is then performed on a predetermined portion of the integrated circuit to detect a set of faulty memory locations. The results of this first BIST run are stored. A second condition is applied to the die and a second BIST run is executed to generate a second set of faulty memory locations. The results of the second BIST run are stored and compared with the first result. If the results differ, the integrated circuit is rejected. Thus, a methodology for screening out field errors at the factory is disclosed using BIST/BISR circuitry.
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Irrinki V. Swamy
Phan Tuan L.
Schwarz William D.
Hoang Huan
LSI Logic Corporation
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