Read leveling of memory units designed to receive access...

Details Read leveling of memory units designed to receive access... Read leveling of memory units designed to receive access...

2008-07-08

2010-10-05

Mai, Son L (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S189070, C714S718000, C714S719000

Reexamination Certificate

active

07808849

ABSTRACT:
Read leveling of memory units designed to receive access requests in a sequential chained topology writing a data pattern to the memory array. In an embodiment, a memory controller first writes a desired pattern into the memory array of a memory unit and then iteratively determines the accurate calibrated delay by setting a compensation delay to a test value, reading a data portion from the memory array based on the test value for the compensation delay, comparing the data portion with an expected data, determining that the test value is a calibrated compensation delay for the memory unit if the data portion equals the expected value.

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“JEDEC Standard”, “DDR3 SDRAM Specification”, Date: Sep. 2007, pp. 1-189.

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