Reduced pin count stress test circuit for integrated memory devi

Details Reduced pin count stress test circuit for integrated memory devi Reduced pin count stress test circuit for integrated memory devi

1995-06-07

1997-01-07

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

36518905, 36523008, G11C 2900

Patent

active

055924220

ABSTRACT:
A circuit and related method are provided internally to an integrated circuit for stress testing its memory. A test mode control circuit, having a first and a second test mode control input, is used, during special test operation mode, to force outputs of address buffers, data buffers and other signal buffers, like chip-enable or write buffers, to predetermined logic values so that all row and column decoders are selected and predetermined data is written into the array of memory cells. Contemporaneously are also exercised entire paths of buffers. The integrated circuit is heated and maintained at an elevated temperature for a desired time, and then cooled down. In this way it is possible, at wafer level, to stress test for ionic contamination, trap sites and weak oxides the integrated circuit in a short time, requiring only a limited number of test signals. For example by connecting only four probes to the integrated circuit (ground, supply voltage and two test mode inputs), it is possible to write all 0's or all 1's and to deselect the entire memory array during the test. This circuit allows to use very simple test equipment and reduces dramatically test times, avoiding consequent burn in of packaged devices.

REFERENCES:
patent: 4860260 (1989-08-01), Saito et al.
patent: 4951254 (1990-08-01), Ontrop et al.
patent: 5315554 (1994-05-01), Nanba
patent: 5339277 (1994-08-01), McClure
patent: 5341336 (1994-08-01), McClure

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