Read/write memory device with an embedded read-only pattern and

Details Read/write memory device with an embedded read-only pattern and Read/write memory device with an embedded read-only pattern and

1987-11-05

1989-06-20

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

365154, 365226, 36518903, G11C 1300

Patent

active

048414859

ABSTRACT:
A memory array device with an embedded self-test binary pattern. The device has an array of bistable cells formed with first and second sides that are oppositely connected to a first voltage line or a second voltage line. If the first and second voltage lines are energized at the same voltage level, each of the bistable cells will function in a normal bistable mode. If the first and second voltage lines are energized at different levels, each of the bistable cells will function in an embedded binary pattern mode.

REFERENCES:
patent: 3805152 (1974-04-01), Ebersman et al.
patent: 3961252 (1976-06-01), Eichelberger
patent: 3961254 (1976-06-01), Cavaliere et al.
patent: 4332028 (1982-05-01), Joccotton et al.
patent: 4481627 (1984-11-01), Beauchesne et al.
patent: 4585955 (1986-04-01), Uchida
patent: 4684826 (1987-08-01), France et al.
IBM Technical Disclosure Bulletin, vol. 23, No. 4, 9/80, "Shared Random-Access Memory and ROS Functions by Modified Random-Access Memory Design", R. J. Prilik.

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