Reconfigurable built-in self test circuit

Details Reconfigurable built-in self test circuit Reconfigurable built-in self test circuit

1997-10-10

1999-11-09

Nguyen, Viet O.

Static information storage and retrieval

Read/write circuit

Testing

371 225, 371 251, G01R 3128

Patent

active

059826819

ABSTRACT:
A reconfigurable built-in self test circuit for enabling the debugging of an embedded device. In one embodiment, the write data path from the built-in self test module to the embedded device includes a multiplexer which is controlled by a debug signal. When the debug signal is de-asserted, the multiplexer forwards the write data from the built-in self test module to the embedded device, thereby allowing the self test to proceed in the hard wired manner. When the debug signal is asserted, the multiplexer forwards external data from the user to the embedded device, thereby allowing the user to execute customized tests on the embedded device. A second multiplexer is similarly placed in the expected data path from the built-in self test module to the comparator to allow the user to provide external data for comparison with output data from the embedded device when the debug signal is asserted. For all tests, the address and control data is provided by the built-in self test module to avoid the need to implement an external access to these data paths.

REFERENCES:
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patent: 5553082 (1996-09-01), Connor et al.
patent: 5568437 (1996-10-01), Jamal
patent: 5617531 (1997-04-01), Crouch et al.
patent: 5764878 (1998-06-01), Kablanian et al.
patent: 5812562 (1998-09-01), Baeg

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