Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2006-02-07
2006-02-07
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000
Reexamination Certificate
active
06996017
ABSTRACT:
The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
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Matrix Semiconductor Inc.
Phung Anh
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