Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
1999-08-12
2001-03-27
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, C365S230060
Reexamination Certificate
active
06208570
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor devices, and more particularly to testing the functionality of redundant memory cells in a semiconductor memory device.
BACKGROUND OF THE INVENTION
Semiconductor memory devices typically include a large number of memory cells, each of which can store one or more bits of data. The memory cells are arranged in an array, having a number of rows and columns. Memory cells within the same row are commonly coupled to a word line, and memory cells within the same column are commonly coupled to a bit line. The memory cells within an array are accessed according to the various memory device operations. Such operations include read operations (common to nearly all memory devices), write operations (common to volatile memory devices), and program and erase operations (common to many nonvolatile memory devices). To access memory cells, an external memory address is applied, which activates a word line. When activated, row decoder circuits couple the data stored within the memory cells to the bit lines of the array. The memory address also activates column decoder circuits, which connect a given group of bit lines to input/output circuits and/or program/erase circuits.
In the course of fabricating a semiconductor memory device, manufacturing defects can give rise to nonfunctional memory cells within an array. In order to preserve the functionality of devices having defective memory cells, redundant memory cells are often used. Redundant memory cells are extra memory cells that are used to replace defective memory cells. A typical redundancy scheme includes row-wise and column-wise redundancy, in which one or more extra rows and/or columns of memory cells are created within the array. In the event an applied memory row address corresponds to a row having a defective memory cell, one of the extra rows of memory cells is accessed in lieu of the row containing the defective memory cell. In the event an applied memory column address corresponds to a column having a defective memory cell, one of the extra columns of memory cells is accessed in lieu of the column containing the defective memory cell. Both redundant row and redundant columns are typically needed in order to efficiently repair certain types of defects. For example, a redundant row is typically used to replace word line shorts and a redundant column is typically used to replace bit line shorts and sense amplifier defects.
It is also desired to test the redundant memory cells in order to detect defects in the redundancy. If a redundant memory cell is defective then the redundant row and/or redundant column that is associated with that cell will not be used to repair a normal defective memory cell. Thus, the overall yield (fully functional chips/chips manufactured) will be improved. In order to reduce test time, it is desirable to test the redundant memory cells in as short a time as possible. Testing is typically done at the wafer level (i.e. after processing, but while individual chips are still embedded on a contiguous silicon wafer), and there may be hundreds or more individual chips on a single silicon wafer. Thus, reductions in test time, which increase throughput, can reduce the cost of manufacturing a memory device by allowing fewer test equipment at the redundancy test procedure (sometimes known as laser probe because a laser may be used to evaporate fusible links). Furthermore, it is desirable to have a simplified testing method in order to make the test programs as simple as possible to reduce possible mistakes or further inefficiencies in the test algorithms.
Referring now to
FIG. 1
, a dynamic random access memory (DRAM) is set forth in a block schematic diagram, and designated by the general reference character
100
. The DRAM
100
includes an address buffer
102
, a design-for-test (DFT) control
104
, a row decoder
106
, and a redundant row decoder
108
. The address buffer
102
receives externally applied address signals (ADD) and in response to control signals (not shown) will apply the address signals to either an internal row address bus (INTRADD) or an internal column address bus (INTCADD). In response to the INTRADD signals, either a normal word line will be activated by way of the row decoder
106
or in the event the internal row address INTRADD corresponds to a defective normal word line, a redundant word line will be activated by way of the redundant row decoder
108
. The activated word line will select a row of memory cells from a memory array
110
, selected of which data may be read from or written to.
The selected row of memory cells are coupled to a bank of sense amplifiers. The bank of sense amplifiers is shown to have a normal sense amplifier bank portion
120
and a redundant sense amplifier bank portion
122
. The sense amplifier bank (
120
and
122
) amplifies a relatively small differential voltage placed on bit lines (not shown) in the array
110
. The internal column address INTCADD is received by a column decoder
124
and a redundant column decoder
126
. In response to the INTCADD signals, either a normal column will be activated by way of column decoder
124
or in the event the internal column address INTCADD corresponds to a defective normal column, a redundant column will be activated by way of the redundant column decoder
126
. The activated row and column will select the memory cells in the array so that data may be read from or written to the selected memory cells by way of external input output lines DQ.
The DRAM
100
further includes a Design-For-Test (DFT) control
104
. The DFT control
104
receives control signals CTRL and the internal row address INTRADD and produces a test row redundancy signal DFTRR and a test column redundancy DFTCR. The DFTRR signal is received by the redundant row decoder
108
and the DFTCR signal is received by the redundant column decoder
126
.
The DFT control circuit
104
allows the redundant rows and redundant columns to be tested before the defective normal rows, defective normal columns and/or defective bits are repaired. The DFT mode is entered by entering a “key address” by way of the externally applied address signals ADD during a DFT entry cycle. The DFT entry cycle is performed by a predetermined sequence of control signals CTRL and may require an “overvoltage” signal (a predetermined voltage level higher than the external voltage supply) on selected of the externally applied address signals. It is noted that the memory array
110
is divided into four sections, a normal section
112
, a redundant row-normal column section
114
, a redundant column-normal row section
116
, and a redundant row-redundant column section
118
. Based on the “key address”, either the DFTRR signal becomes active in order to test the redundant row-normal column section
114
in the memory array
110
, or the DFTCR signal becomes active in order to test the redundant column-normal row section
116
in the memory array
110
, or both the DFTRR signal and DFTCR signal become active in order to test the redundant row-redundant column section
118
in the memory array
110
.
It is noted that three different DFT modes are required in order to test all the redundant cells in the memory array
110
. Furthermore, a DFT clear cycle may be required before entering the next DFT mode, especially in the event the DFT mode is made to be concurrent (i.e. capable of being entered along with other DFT modes being active). This requires the test algorithm to be complicated and for test time to be lengthened, thus creating a greater potential for error and decreasing the throughput in testing the memory device. This can be greater understood in view of FIG.
2
.
FIG. 2
sets forth a test sequence that may be used to test the memory device set forth in FIG.
1
. First, the normal array
110
may be tested by operating the DRAM
100
in a normal operating mode, or alternatively a parallel test DFT mode may be entered in order to test a greater number of bits than normal in one cycle. After all of the normal a
Brown Brian L.
Brown David R.
Brady III Wade James
Elms Richard
Nguyen Vanthu
Stewart Alan K.
Telecky , Jr. Frederick J.
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