Read complete test technique for memory arrays

Details Read complete test technique for memory arrays Read complete test technique for memory arrays

1985-10-30

1987-08-25

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

371 21, 371 51, G11C 1140

Patent

active

046897720

ABSTRACT:
A circuit and method for generating a read complete signal for a high speed densely packaged monolithic memory is disclosed. The memory is designed to utilize an externally generated address valid signal which indicates that the address to the memory is valid. The receipt of the address valid signal sets a set/reset latch and starts the memory. The addressed memory cells are sensed. When at least one memory cell has data at its output below a threshold, the data are said to be unstable and the set/reset latch is then conditioned to be reset. When the data sensed by all the sensing circuits are stable, a signal is sent to the set/reset latch to cause it to be reset. The resetting of the set/reset latch causes an output thereof to change state. This state change comprises the read complete signal which is used to determine the read cycle time of the memory and may also be used in diagnostic tests of the memory.

REFERENCES:
patent: 3795901 (1974-03-01), Boehm et al.
patent: 3982111 (1976-09-01), Lerner et al.
patent: 4004222 (1977-01-01), Gebhard
patent: 4380805 (1983-04-01), Proebsting
"Functional and Level Fail Detection for Register Array Testing" by P. P. Heavey and V. E. Simpson, IBM Technical Disclosure Bulletin, vol. 15, No. 4, Sep. 1972, pp. 1135-1136.

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