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Damascene-gate process for the fabrication of MOSFET devices...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Data bus architecture for integrated circuit devices having...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Data retention of EEPROM cell with shallow trench isolation usin

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Data writing method for mask read only memory

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Decoder for a stationary switch machine

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Decoupled complementary mask patterning transfer method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Decoupling capacitor for high frequency noise immunity

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Deep buried channel junction field effect transistor (DBCJFET)

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate
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Deep buried channel junction field effect transistor (DBCJFET)

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate
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Deep junction SOI MOSFET with enhanced edge body contacts

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Deep pivot mask for enhanced buried-channel PFET performance and

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Deep sub-micron polysilicon gap formation

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Deep submicron MOS transistor with increased threshold voltage

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Deep submicron MOSFET device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Deep trench capacitor and method of fabricating the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Deep trench capacitor having increased surface area

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Deep trench capacitor through SOI substrate and methods of...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Deep trench device with single sided connecting structure...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Deep trench dram process on SOI for low leakage DRAM cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Deep trench isolation of embedded DRAM for improved latch-up...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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