Data bus architecture for integrated circuit devices having...

Details Data bus architecture for integrated circuit devices having... Data bus architecture for integrated circuit devices having...

2000-08-31

2002-10-01

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S241000, C438S253000, C365S052000, C365S063000, C365S189050, C365S201000, C365S230010

Reexamination Certificate

active

06458644

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit devices. More particularly, the present invention relates to a data bus architecture for integrated circuit embedded dynamic random access memory (“DRAM”) having a large aspect ratio (length to width ratio) which serves to reduce power requirements in the data path through the use of multiple metal layers to reduce capacitance on the data busses.
High density embedded DRAM is often required to be integrated on-chip with other integrated circuit devices and circuits. In certain applications, the aspect ratio of the embedded DRAM (or macro) must be relatively large. That is, it must be long and narrow to be properly integrated on the device substrate. In applications where a relatively large amount of fast access time DRAM is required, such as a graphics IC, a comparatively large number of such macros must be placed on-chip. Moreover, depending upon the particular application, all of the embedded DRAM's input/output (“I/O”) terminals (as well as other control inputs) may need to be located along the narrow width of the macro. Utilizing conventional layout techniques, these architectural requirements are extremely difficult to achieve given the resulting long signal lines required. This is particularly the case when the constraints of high speed operation and low power supply requirements are imposed.
SUMMARY OF THE INVENTION
The data bus architecture disclosed herein is particularly advantageous for use in addressing data bussing problems inherent in integrated circuit devices having embedded DRAM with a large aspect ratio and requiring a relatively large number of input/outputs (“I/Os”) to be located along one narrow side of the memory. In accordance with the disclosure herein, the memory is divided into multiple sections with data bussing in those sections routed in one metal, or conductive, layer. A different metal layer is used to route global data across these sections to a data register located on one edge of the memory. These global data lines are double data rate (“DDR”) and single-ended (as opposed to differential-ended) which increases the physical spacing of these lines thereby reducing capacitance and power requirements. Moreover, each of the global data lines are routed to only one of the memory sections. This results in the average length of these lines being less than the length of the entire memory which further serves to reduce the capacitance of the lines.
Particularly disclosed herein is an integrated circuit device incorporating an embedded memory which comprises a plurality of memory arrays disposed substantially linearly about a common axis and a like plurality of memory array data registers, each of the memory array data registers coupled to, and associated with, one of the plurality of memory arrays and disposed adjacent a first edge thereof substantially perpendicularly about the common axis. A common data register is disposed substantially perpendicularly about the common axis and is coupled to the plurality of memory array data registers by a plurality of global data lines. A first subset of the plurality of global data lines extends only to an adjacent one of the plurality of memory arrays and a second subset extends over the adjacent memory array to a nextmost adjacent one of the plurality of memory arrays. A third subset further extends over the adjacent and nextmost adjacent one or the memory arrays to another memory array.
Also disclosed herein is a method for reducing data line capacitance in an integrated circuit device having a plurality of conductive layers formed therein and incorporating a memory array having a plurality of word lines (or word line shunts), data lines and global data lines coupled to the data lines. The method comprises forming the word lines in an n
th
layer of the plurality of conductive layers and forming the data lines in an (n+2)
th
layer of the plurality of conductive layers and forming the global data lines in the (n+4)th layer of the plurality of conductive layers.


REFERENCES:
patent: 5388073 (1995-02-01), Usami et al.
patent: 5440516 (1995-08-01), Slemmer
patent: 5991224 (1999-11-01), Aipperspach et al.
patent: 5998251 (1999-12-01), Wu et al.

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