Data retention of EEPROM cell with shallow trench isolation usin

Details Data retention of EEPROM cell with shallow trench isolation usin Data retention of EEPROM cell with shallow trench isolation usin

1997-10-09

1998-12-29

Dang, Trung

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438248, 438424, 438435, 438257, H01L 21336

Patent

active

058541144

ABSTRACT:
A shallow trench isolation structure and a method for forming the same for use with non-volatile memory devices is provided so as to maintain sufficient data retention thereof. An epitaxial layer is formed on a top surface of a semiconductor substrate. A barrier oxide layer is formed on a top surface of the epitaxial layer. A nitride layer is deposited on a top surface of the barrier oxide layer. Trenches are formed through the epitaxial layer and the barrier oxide layer to a depth greater than 4000 .ANG. below the surface of the epitaxial layer so as to create isolation regions in order to electrically isolate active regions in the epitaxial layer. A liner oxide is formed on sidewalls and bottom of the trenches to a thickness between 750 .ANG. to 1500 .ANG.. As a result, leakage current in the sidewalls are prevented due to less thinning of the liner oxide layer by subsequent fabrication process steps.

REFERENCES:
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 5008722 (1991-04-01), Esquivel
patent: 5040036 (1991-08-01), Hazani
patent: 5042008 (1991-08-01), Iwasa et al.
patent: 5229312 (1993-07-01), Mukherjee et al.

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