Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-28
2002-08-27
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S592000, C438S926000
Reexamination Certificate
active
06440808
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor processing, and more particular to a process for fabricating a high-performance sub-0.1 &mgr;m metal oxide semiconductor field effect transistor (MOSFET) device having minimum polysilicon-, i.e., poly-, depletion, silicided source and drain junctions and very low sheet resistance (on the order of 5 ohm/sq. or less) poly-gates.
BACKGROUND OF THE INVENTION
In conventional complementary metal oxide semiconductor (CMOS) processes, the MOSFET's source, drain and gate regions are implanted simultaneously, activated annealed and thereafter silicided so as to produce low junction regions in the substrate and poly-gate lines with low sheet resistance.
For high-performance sub-0.1 &mgr;m CMOS devices, these conventional CMOS processes result in the following two problems. The first problem is caused by the simultaneous implantation of the source, drain and gate regions. To guarantee shallow source and drain junctions after annealing, low-implant doses (on the order of 2E15/cm
2
or less) are typically used. These low-implant doses however are not sufficient to prevent poly-gate depletion which, if not prevented, causes low device transconductance and reduced device performance.
The second problem with the prior art CMOS processes mentioned above is caused by the mere process of siliciding the poly-gate. For poly-gates having a width of 0.25 &mgr;m or less, nucleation limited growth of the silicided polysilicon, e.g., TiSi, results in very high sheet resistance which causes an even further reduction in device performance.
In view of the drawbacks mentioned above concerning conventional CMOS processing of high performance sub-0.1 &mgr;m CMOS devices, there is a continued need for developing a new and improved process which enables the fabrication of high performance sub-0.1 &mgr;m CMOS devices without those devices exhibiting poly-gate depletion and high sheet resistance.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a process which enables the decoupling of the gate implantation and activation annealing from the source and drain implantation and activation annealing.
Another object of the present invention is to provide a process which provides for a very low poly-gate sheet resistance that is independent of the silicidation process of the source and drain regions.
These and other objects and advantages can be achieved in the present invention by utilizing a damascene-gate processing technique which includes the use of a dummy gate region which is present during implanting, activation annealing and siliciding the source and drain regions, the subsequent removal of the dummy gate region and the formation of a metal- or poly-gate region in the region previously occupied by the dummy gate.
Specifically, the process of the present invention comprises the steps of:
(a) providing a dummy gate region on a surface of a substrate, said dummy gate region including polysilicon sandwiched between a bottom oxide layer and a top oxide layer;
(b) forming activated source and drain regions in said substrate using said dummy gate region as an implantation mask;
(c) siliciding the surface of said substrate overlying said activated source and drain regions;
(d) forming an insulator layer on said surface of said substrate, said insulator layer also surrounding said dummy gate region;
(e) planarizing said insulator layer so as to remove said top oxide layer of said dummy gate region thus exposing said polysilicon;
(f) selectively removing said polysilicon and said bottom oxide layer of said dummy gate region so as to provide an opening which exposes a portion of said substrate;
(g) forming a gate dielectric on said exposed portion of said substrate;
(h) depositing a gate conductor on said gate dielectric; and
(i) etching said insulator layer formed in step (d).
In one embodiment of the present invention, a recessed polysilicon layer is formed on the gate dielectric prior to conducting steps (h) and (i). The polysilicon of the recessed polysilicon layer may be formed by an in-situ doping deposition process or, alternatively, the polysilicon may be intrinsic polysilicon that is doped by subsequent ion implantation and annealing. The in-situ doping process is employed when a high temperature sensitive gate dielectric is employed, whereas ion implantation and annealing are employed when the gate dielectric consists of a material that can withstand high temperature annealing. It should be noted that when ion implantation and annealing are employed, no silicide agglomerization occurs since the silicide region is protected by the insulator layer that is deposited thereon prior to ion implantation and annealing.
In another embodiment of the present invention, an optional liner is formed on the gate dielectric and on exposed sidewalls of the opening prior to depositing the gate conductor.
In yet another embodiment, heavily N+ doped polysilicon is used as the dummy gate. This embodiment of the present invention enables the dummy gate to be wet etched.
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patent: 6284613 (2001-09-01), Subrahmanyam et al.
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Boyd Diane Catherine
Brodsky Stephen Bruce
Hanafi Hussein Ibrahim
Roy Ronnen Andrew
Niebling John F.
Schecter Manny W.
Scully Scott Murphy & Presser
Whitemore Stacy
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