Deep pivot mask for enhanced buried-channel PFET performance and

Details Deep pivot mask for enhanced buried-channel PFET performance and Deep pivot mask for enhanced buried-channel PFET performance and

1998-10-29

2000-10-03

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438391, 438421, 438424, 438427, 438700, 438701, 257369, 257374, H01L 218238, H01L 2176

Patent

active

061272159

ABSTRACT:
A semiconductor structure comprises first gate conductors which wrap around N-wells of buried-channel P-type metal oxide semiconductor field effect transistors and second gate conductors which do not wrap around P-wells of surface-channel N-type metal oxide semiconductor field effect transistors and a method of manufacturing the same comprises forming insulators adjacent each of the N-wells and the P-wells, protecting the N-wells with a patterned mask, forming first divots in areas of the insulators adjacent the N-wells and forming second divots in areas of the insulators adjacent P-wells, wherein the first divots have a greater depth than the second divots.

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