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FinFET SRAM cell using low mobility plane for cell stability...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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FinFET structures with stress-inducing source/drain-forming...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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FinFET transistor and circuit

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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FinFET transistor and circuit

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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FinFET transistor and circuit

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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FinFET transistor device on SOI and method of fabrication

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Finfet transistor structures having a double gate channel...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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FinFET with sublithographic fin width

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Finfet/trigate stress-memorization method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Finfet/trigate stress-memorization method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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FinFETs (Fin Field Effect Transistors)

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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finFETS and methods of making same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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FinFETs with long gate length at high density

Semiconductor device manufacturing: process – Making field effect device having pair of active regions...
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Finned memory cells and the fabrication thereof

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Fipos method of forming SOI CMOS structure

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Five channel fin transistor and method for fabricating the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Flash assisted annealing

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Flash device and the manufacturing method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Flash EEPROM

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Flash EEPROM cell and method of manufacturing the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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