Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-09-29
2000-08-22
Booth, Richard
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438257, H01L 218247
Patent
active
061071412
ABSTRACT:
An EEPROM cell includes a dual-gate transistor having a floating gate for storing the data and a select gate to access the cell, the two gates each being formed from poly sidewalls and being separated by a thin vertical oxide member that is formed by growing oxide on the vertical poly sidewalls of an aperture in which the select gate is formed, so that the final structure has dimensions that are less than those obtainable with optical lithography because both gates are sidewalls and therefore not limited to the dimensions achievable with optical lithography.
REFERENCES:
patent: 5494838 (1996-02-01), Chang et al.
patent: 5989960 (1999-11-01), Fukase
patent: 5998263 (1999-12-01), Sekariapuram et al.
Hsieh Chang-Ming
Hsu Louis Lu-Chen
Ogura Seiki
Booth Richard
International Business Machines - Corporation
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