Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-10-23
2002-07-02
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S283000
Reexamination Certificate
active
06413802
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to FET and MOSFET transistors, and more particularly the invention relates to field effect transistors having channel regions extending vertically from a supporting substrate between horizontally disposed source and drain regions.
Metal-Oxide-Semiconductor field effect transistor (MOSFET) technology is the dominant electronic device technology in use today. Performance enhancement between generations of devices is generally achieved by reducing the size of the device, resulting in an enhancement in device speed. This is generally referred to as device “scaling”. As MOSFETs are scaled to channel lengths below 100 nm, conventional MOSFETs suffer from several problems. In particular, interactions between the source and drain of the MOSFET degrade the ability of the gate of the same to control whether the device is on or off. This phenomenon is called the “short-channel effect”. Silicon-on-insulator (SOI) MOSFETs are formed with an insulator (usually, but not limited to, silicon dioxide) below the device active region, unlike conventional “bulk” MOSFETs, which are formed directly on silicon substrates, and hence have silicon below the active region. SOI is advantageous since it reduces unwanted coupling between the source and the drain of the MOSFET through the region below the channel. This is often achieved by ensuring that all the silicon in the MOSFET channel region can be either inverted or depleted by the gate (called a fully depleted SOI MOSFET). As device size is scaled, however, this becomes increasingly difficult, since the distance between the source and drain is reduced, and hence, they increasing interact with the channel, reducing gate control and increasing short channel effects (SCE).
The double-gate MOSFET structure is promising since it places a second gate in the device, such that there is a gate on either side of the channel. This allows gate control of the channel from both sides, reducing SCE. Additionally, when the device is turned on using both gates, two conduction (“inversion”) layers are formed, allowing for more current flow. An extension of the double-gate concept is the “surround-gate” or “wraparound-gate” concept, where the gate is placed such that it completely or almost-completely surrounds the channel, providing better gate control.
Leobandung et al. and J. Vac. Sci. Technol. B 15(6), November/December 1997, pp. 2791-2794 disclose a wire channel and wraparound gate metal oxide semiconductor field effect transistor. In this structure spaced source and drain regions support a silicon “wire” above a substrate with a four-sided gate surrounding the wire channel region. The suspended channel region limits the device dimensions and the four-sided wraparound gate is prone to comer effects and mobility degradation due to electric fields penetrating the channel from all directions.
Hisamoto et al. IEDM 98, pp. 1032-1034 and Huang et al. IEDM 97, pp. 67-70 disclose FinFET structures in which the channels are first formed and then source and drain regions are formed by a silicon deposition process. This results in source and drain which are necessarily taller than the channel fin, and the gate length is defined by using an oxide spatial process to create a gap between the tall source and drain islands. This gap is then filled with gate material such as the gate straddles the fin and forms a double gate device. Thus in this structure the channel link is defined by the spacer definition process rather than by lithographic patterning, requiring a complicated process.
The present invention is directed to a process for fabricating FinFET transistor structures which is an extension of conventional planar MOSFET technology and resulting structures.
SUMMARY OF THE INVENTION
In accordance with the invention a method is provided for fabricating a double gate field effect transistor (FinFET) which is compatible with conventional MOSFET fabrication processes. The device channel comprises a thin silicon fin standing on an insulative layer (e.g. silicon oxide) with the gate overlying the sides of the fin. Thus inversion layers are formed on the sides of the channel with the channel film being sufficiently thin such that the two gates control the entire channel film and limit modulation of channel conductivity by the source and drain. In a preferred embodiment, the thickness of the film is chosen such that it is less or equal to {fraction (7/10)}ths of the channel length. In most implementations the channel film width is less than the channel length such that the channel of the device resembles a long thin film.
The double gates on the channel fin effectively suppress SCE and enhance drive current. In some embodiments, a plurality of channels can be provided between source and drain regions and since the channel is thin and the fins are parallel, vertical fields are reduced thereby reducing the degradation and mobility typically caused by vertical fields. Further, since the fin is thin, doping of the fin is not required to suppress SCE and undoped silicon can be used as the device channel, thereby reducing mobility degradation due to impurity scattering. Further, the threshold voltage of the device may be controlled by adjusting the work function of the gate by using a silicon-germanium alloy or a refractory metal or its compound such as titanium nitride.
In an alternative embodiment of the invention, stacked transistors can be provided with a single gate overlapping the channel fins of the transistors.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawings.
REFERENCES:
patent: 5356824 (1994-10-01), Chouan et al.
patent: 5604368 (1997-02-01), Taur et al.
patent: 5646058 (1997-07-01), Taur et al.
patent: 5773331 (1998-06-01), Solomon et al.
patent: 5804848 (1998-09-01), Mukai
patent: 5899710 (1999-05-01), Mukai
patent: 6214670 (2001-04-01), Shih et al.
V. Subramanian et al., “A Bulk-Si-compatible Ultrathin-body SOI Technology for sub-100nm MOSFETS,” Proceedings of the 57th Annual Device Research Conference, pp. 28-29 (1999).
Hisamoto et al., “A Folded-channel MOSFET for Deep-sub-tenth Micron Era,” 1998 IEEE International Electron Device Meeting Technical Digest, pp. 1032-1034 (1998).
Huang et al., “Sub 50-nm FinFET: PMOS,” 1999 IEEE International Electron Device Meeting Technical Digest, pp. 67-70 (1999).
Auth et al., Vertical, Fully-Depleted, Surrounding Gate MOSFETS on sub-0.1&mgr;m Thick Silicon Pillars, 1996 54th Annual Device Research Conference Digest, pp. 108-109 (1996).
Hisamoto et al., “A Fully Depleted Lean-Channel Transistor (DELTA)—A Novel Vertial Ultrathin SOI MOSFET,” IEEE Electron Device Letters, v. 11(1), pp. 36-38 (1990).
Leobandung et al., “Wire-channel and wrap-around-gate metal-oxide-semiconductor field-effect transistors with a significant reduction of short channel effects,” J. Vac. Sci. Technol. B 15(6), pp. 2791-2794 (1997).
Auth et al., Vertical, Fully-Depleted, Surrounding Gate MOSFETS on sub-0.1&mgr;m Thick Silicon Pillars, 1996 54th Annual Device Research Conference Digest, pp. 108-109 (1996).
Bokor Jeffrey
Chang Leland
Choi Yang-Kyu
Hu Chenming
Huang Xuejue
Dang Phuc T.
The Regents of the University of California
Townsend and Townsend / and Crew LLP
Woodward Henry K.
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