Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2009-09-17
2011-10-25
Stark, Jarrett (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C257S347000, C257S401000
Reexamination Certificate
active
08043920
ABSTRACT:
A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.
REFERENCES:
patent: 7199419 (2007-04-01), Haller
patent: 7692254 (2010-04-01), Anderson et al.
patent: 7851865 (2010-12-01), Anderson et al.
patent: 2011/0049583 (2011-03-01), Lin et al.
Chan Kevin K.
Kanarsky Thomas Safron
Li Jinghong
Ouyang Christine Qiqing
Park Dae-Gyu
International Business Machines - Corporation
Schmeiser Olsen & Watts
Stark Jarrett
Tobergte Nicholas
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