FinFET with sublithographic fin width

Details FinFET with sublithographic fin width FinFET with sublithographic fin width

2007-07-26

2009-12-01

Smith, Matthew (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21001

Reexamination Certificate

active

07625790

ABSTRACT:
At least one recessed region having two parallel edges is formed in an insulator layer over a semiconductor layer such that the lengthwise direction of the recessed region coincides with optimal carrier mobility surfaces of the semiconductor material in the semiconductor layer for finFETs to be formed. Self-assembling block copolymers are applied within the at least one recessed region and annealed to form a set of parallel polymer block lines having a sublithographic width and containing a first polymeric block component. The pattern of sublithographic width lines is transferred into the semiconductor layer employing the set of parallel polymer block lines as an etch mask. Sublithographic width semiconductor fins thus formed may have sidewalls for optimal carrier mobility for p-type finFETs and n-type finFETs.

REFERENCES:
patent: 2006/0134556 (2006-06-01), Nealey et al.
patent: 2006/0175667 (2006-08-01), Tsuchiaki
patent: 2007/0001173 (2007-01-01), Brask et al.
Yang, Haining, U.S. Appl. No. 11/424,963, filed Jun. 19, 2006, Title: “Sub-Lithographic Feature Patterning Using Self-Aligned Self-Assembly Polymers”.
Nealey, Paul F. et al., “Self-assembling resists for nanolithography”, IEDM Technical Digest, Dec. 2005, Digital Object Identifier 10.1109/IEDM.2005.1609349.

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