FinFET transistor device on SOI and method of fabrication

Details FinFET transistor device on SOI and method of fabrication FinFET transistor device on SOI and method of fabrication

2007-11-27

2007-11-27

Whitehead, Carl (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S269000, C438S300000, C438S607000

Reexamination Certificate

active

10836295

ABSTRACT:
A FinFET transistor on SOI device and method of fabrication is provided. At least two FinFET fins each having an upper poly-silicate glass portion and a lower silicon portion are formed using spacer patterning technology. Each fin is formed on a sacrificial SiN mask layer having a sacrificial support structure. The SiN mask is removed and then a breakthrough etch is applied to remove an underlying pad oxide layer. A PSG layer defining a width of each of the fins on a sidewall of each of the support structures is deposited on each of the support structures. At least two fins each having a narrow fin pitch of about 0.25 μm. are formed. The fins provide a seed layer for at least two selective epitaxially raised source and drain regions, wherein each raised source-drain associated with each fin are interconnected thus forming a source pad and a drain pad.

REFERENCES:
patent: 6872647 (2005-03-01), Yu et al.
patent: 6936875 (2005-08-01), Sugii et al.
patent: 2005/0035415 (2005-02-01), Yeo et al.
Chang et al, “Extremely Scaled Silicon Nano-CMOS Devices.” Proceedings of the IEEE, vol. 91, No. 11, 2003, pp. 1860-1873.
Kedzierski et al, “High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices,” IEEE, 2001, pp. 19.5.1-19.5.4.

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