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Embedded DRAM integrated circuits with extremely thin...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Embedded DRAM on silicon-on-insulator substrate

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Embedded dual-port DRAM process

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Embedded memory logic device using self-aligned silicide and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Embedded NV memory and method of manufacturing the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Embedded ROM device using substrate leakage

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Embedded ROM device using substrate leakage

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Embedded strain layer in thin SOI transistors and a method...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Embedded strain layer in thin SOI transistors and a method...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Embedded stressed nitride liners for CMOS performance...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Embedded stressor structure and process

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Embedded vertical DRAM cells and dual workfunction logic gates

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Encapsulated spacer with low dielectric constant material to...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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End-of-range defect minimization in semiconductor device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Engineered metal gate electrode

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Enhanced cap layer integrity in a high-K metal gate stack by...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Enhanced capacitor shape

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Enhanced integrity of a high-K metal gate electrode...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Enhanced multi-bit non-volatile memory device with resonant...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Enhanced oxynitride gate dielectrics using NF.sub.3 gas

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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