Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-18
2001-04-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S155000, C257S350000
Reexamination Certificate
active
06214676
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to an embedded memory logic device using self-aligned silicide and a manufacturing method therefor.
2. Description of the Related Art
As semiconductor devices become more highly integrated, silicon on chip (SOC) devices have been introduced, in which many devices having various functions are integrated into one chip so that they interactively operate. It is more complicated and difficult to manufacture an SOC device. In order to integrate two or more devices having different functions into one chip, characteristics required for each of the devices must be realized simultaneously. Accordingly, the process becomes more complicated, and depending on the circumstances, additional processes may be required.
An embedded memory logic (EML) device, which is a type of SOC device, is obtained by integrating a memory device and a logic device into one chip. An EML device is composed of a cell array region and a logic circuit region. A plurality of memory cells are located in the cell array region and information stored in the cell array region is operated on by the logic circuit, thereby generating new information. DRAM cells or SRAM cells are widely used for the memory cells.
Effective prevention of leakage current is required as a key characteristic of the access transistors in the cell array region. Meanwhile, transistors in a peripheral circuit region need excellent current driving ability rather than leakage current prevention, since the current driving ability of these transistors determines the overall performance of the chip.
An embedded DRAM logic (EDL) device adopts DRAM cells as memory cells. In an EDL device, information charge stored in the memory cells is lost due to the leakage current. Accordingly, an operation for periodically refreshing the information is required. To improve the refresh characteristics, two main methods are used. In a first method, the capacitance of storage capacitors are increased to maintain data even though the leakage current exists. In a second method, the leakage current is reduced to maintain the stored charge.
In order to enhance the operational speed of an EDL device, a self-aligned silicide (salicide) process has been widely used. With the salicide process, a metal silicide layer having low resistivity, such as titanium silicide, is selectively formed on the gate electrode of a transistor and the source/drain region thereof.
In a conventional salicide process, titanium silicide (TiSi2) is formed on the surfaces of the gate electrodes, as well as the source/drains of NMOS transistors in the peripheral circuit portion which are heavily doped with an N-type impurity. Also, in PMOS transistors in the peripheral circuit portion, titanium silicide (TiSi2) is formed on the surfaces of the gates, as well as the source/drain which are doped with a P+ impurity. Accordingly, the resistance of the gate electrode and source/drain are reduced, which enhances current driving ability. In the same manner, titanium silicide is also formed on the surfaces of the source/drains and of the gates of NMOS transistors in the cell array region. However, this titanium silicide causes an increase of junction leakage current. The reason is as follows.
In a conventional salicide process, N+ impurities are implanted into a cell array region to form the source/drain of a memory cell transistor. However, ion-implantation damages the source/drain region. The ion-implantation damage causes crystalline defects such as dislocation, which result in increased junction leakage current between the source/drain and the P-well. When junction leakage current is increased between the P-well and the source or drain of a cell array region connected to a storage electrode of a cell capacitor, the charge stored in the storage electrode is lost quicker. Accordingly, in order to maintain the charge on the storage electrode for a predetermined time, the refresh time, i.e., the time interval between refresh cycles, must be short, and therefore, the power consumption of the device is increased accordingly.
Furthermore, a silicide layer formed on the surface of the source/drains in the cell array region causes stress in the source/drain region, which further increases crystalline defects in the heavily-doped source/drain. Therefore, the junction leakage current is increased further.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide an embedded memory logic device in which junction leakage current of a source/drain formed in a cell array region is reduced to enhance the device characteristics.
It is another object of the present invention to provide a manufacturing method of the embedded memory logic device.
Accordingly, to achieve the first object, there is provided an embedded memory logic device. The embedded memory logic device includes a semiconductor substrate including first and second regions. A first gate electrode is formed on the first region of the semiconductor substrate. A first drain region doped with a first impurity is formed in the semiconductor substrate on one side of the first gate electrode, and a first source region doped with a second impurity is formed in the semiconductor substrate on the other side of the first gate electrode.
A second gate electrode is formed on the second region of the semiconductor substrate, and second source/drain regions doped with a third impurity are formed in the semiconductor substrate on both sides of the second gate electrode. A third gate electrode is formed on the second region of the semiconductor substrate, and third source/drain regions doped with a fourth impurity are formed on both sides of the third gate electrode. Metal silicide layers are formed on the surfaces of the first through third gate electrodes, the first drain, and the second and the third source/drain regions.
The first region is a memory cell array region, and the second region is a peripheral circuit region. The first source region is connected to a storage electrode of a capacitor, and the first drain region is connected to a bit line.
To achieve the second object, there is provided a manufacturing method of an embedded memory logic device. By the method, first through third gate electrodes including a gate insulating layer are formed respectively over first through third regions of a semiconductor substrate. The first through third source/drain regions doped with the first impurity are formed in the semiconductor substrate on both sides of the first through third gate electrodes, respectively. An insulating layer is formed on the entire surface of the resultant structure having the first through the third source/drain regions. A photoresist layer pattern, exposing a region excluding the first region, is formed on the insulating layer. Then, spacers are formed on the sidewalls of a gate electrode formed in a region excluding the first region, by anisotropically etching the insulating layer. The first and second gate electrodes, a first drain region and a second source/drain region, are doped with a second impurity. The third gate electrode and the third source/drain regions are doped with a third impurity. Then, silicide layers are formed on the first through third gate electrodes, the second and third source/drain regions and the first drain, through a salicide process.
The first region is a region between a gate electrode of an access transistor in a memory cell and that of a pass transistor therein, and has a portion in contact with the storage electrode of a memory capacitor. The second region is an NMOS region including a memory cell, and the third region is a PMOS region.
To achieve the second object, there is provided another manufacturing method of an embedded memory logic device. By the method, first through third gate electrodes including a gate insulating layer are formed over the first through third regions of a semiconductor substrate. Then, first thro
Jun In-kyun
Kang Myeon-koo
Kim Young-pil
Park Hyung-Moo
Lee Calvin
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Smith Matthew
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