Embedded dual-port DRAM process

Details Embedded dual-port DRAM process Embedded dual-port DRAM process

2003-05-15

2004-09-21

Thompson, Craig A. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06794254

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to an integrated circuit memory device, and, more particularly, to a method to form dual-port DRAM cells in an integrated circuit device.
(2) Description of the Prior Art
Modern multimedia applications and personal computers require large RAM memory systems with high throughput rates. In particular, three-dimensional graphics rendering and networking applications demand a combination of fast random access cycle times, low latency, and large memory sizes.
Referring now to
FIG. 1
, a plot is shown of typical RAM capacities (bits) versus random access cycle frequency (Hz). It is found that the largest capacities can be formed in dynamic RAM (DRAM) technologies
10
. However, these DRAM technologies are limited in their random access operating speed to the 10 MHz to 100 MHz range. It is also found that the fastest random cycle speeds are achieved using static RAM (SRAM) technology
18
. However, the relatively large cell size of SRAM limits the capacity to about 1 Mbit. Further, it is found that a large number of applications
14
, such as multimedia and networking, would be optimally served by a technology having an operating speed greater than DRAM
10
and a size greater than SRAM
18
. The teachings of the present invention are directed to filling this niche, especially for system on chip (SOC) architectures.
Referring now to
FIG. 2
, a typical DRAM cell construction is shown. A typical DRAM cell comprises a storage capacitor
26
and an access transistor
22
. Most prior art DRAM cells use a MOS transistor
22
as the access device. Many variations on storage capacitors
26
have been described in the art. The source of the access transistor
22
is coupled to the storage capacitor
26
. The drain of the access transistor
22
is coupled to a bit line (BL)
34
. The gate of the access transistor
22
is coupled to a word line (WL)
30
. The voltage, or charge, state of the storage capacitor
26
determines the memory state of the cell. The access transistor
22
is turned ON or OFF by the WL
30
voltage. To write data to the cell, the WL signal
30
is asserted to turn ON the access transistor
22
. The voltage on the BL signal is then coupled to the capacitor
26
. To read the cell, the access transistor
22
is again turned ON by the WL signal
30
. Charge on the capacitor
26
is then coupled onto the BL
34
. A sense amplifier on the BL
34
is used to determine the capacitor voltage and, thereby, the memory value (0 or 1). In addition, the capacitor
26
must be refreshed periodically to compensate for current leakage. A refresh cycle performs a READ of the cell and then a WRITE of the cell to refresh the charge state of the capacitor.
The timing performance of this typical DRAM cell is shown. The BL signal
34
performs in one of two states, ACTIVE and PRECHARGE. During the ACTIVE state, the BL signal
34
is either forcing the WRITE voltage (high or low) to the cell or is conducting the READ charge from the cell. During the PRECHARGE state, the BL signal
34
is forced to a mid-level (between low and high) voltage that is most conducive to low leakage current and to rapid WRITE/READ access. The BL signal
34
transitions from the PRECHARGE state to the ACTIVE state in response to commands (CMD) such as READ or WRITE or REFRESH that are issued by the DRAM control logic. The access cycle time is shown as the time between consecutive accesses to the DRAM cell.
Referring now to
FIG. 3
, another prior art DRAM cell is shown. In this cell, two access transistors
40
and
44
are used to control access to a single storage capacitor
48
. This configuration is called dual-port DRAM. The dual-port DRAM uses a first WL signal, WLa
60
, to control coupling of a first BL signal, BLa
52
, to the capacitor
48
via a first transistor
40
. A second WL signal, WLb
64
, is used to control coupling of a second BL signal, BLb
56
, to the capacitor
48
via a second transistor
44
. The key advantage of the dual-port DRAM cell is increased speed.
The timing diagram shows that the two access BL signals, BLa
52
and BLb
56
, work somewhat independently. When BLa is in the ACTIVE state in response to a CMD, BLb can be in PRECHARGE and visa versa. As a result, it is possible to access the storage capacitor
48
at twice the rate of the single-port DRAM cell of FIG.
2
. While the access rate of the dual-port DRAM is doubled, the cell area is not doubled. The largest element in a DRAM cell is the storage capacitor. While the dual-port DRAM doubles the number of access transistors
40
and
44
, it only requires a single storage capacitor
48
. Because of the improved performance, the dual-port DRAM can offer significant advantages in the multimedia and networking regime of operation
14
described in FIG.
3
. In addition, it is found that significant cost advantages can be achieved by integrating dual-port DRAM memory onto multimedia or networking chips in SOC architectures. To facilitate this multiple technology up-integration, the ability to form high performance logic, I/O, and dual-port DRAM onto a single integrated circuit device is necessary. The integration of these technologies is the focus of the present invention.
Several prior art inventions relate to DRAM cells and to shallow trench isolation structures. U.S. Pat. No. 5,249,165 to Toda describes a multiple port memory device. U.S. Pat. No. 5,811,347 to Gardner et al teaches a method to form shallow trench isolation (STI). Nitrogen is incorporated into the trench liner oxide to thereby improve performance and reduce active area loss. U.S. Pat. No. 6,323,106 B1 to Huang et al describes a method to form STI regions. A liner oxide is formed in the trenches. A tilted angle, ion implantation of nitrogen is performed to form an oxynitride layer in the liner oxide of the trench sidewalls. U.S. Pat. No. 5,327,375 to Harari discloses a DRAM cell with a sidewall storage capacitor. Multiple port DRAM cells and trench capacitors are disclosed. Agata et al, in “An 8-ns Random Cycle Embedded RAM Macro With Dual-Port Interleaved DRAM Architecture (D
2
RAM), IEEE Journal of Solid-State Circuits, Vol. 35, No. 11, November 2000, pp. 1668-1672, discloses a dual-port DRAM device with cells comprising one capacitor and two access transistors. Folded bitline architecture is described.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method to form dual-port DRAM in an integrated circuit device.
A further object of the present invention is to provide a method to form dual-port DRAM in a standard CMOS process while making minimal changes to that process.
A yet further object of the present invention is to provide a method to form dual-port DRAM cells having minimal cell area and optimal access speed.
A yet further object of the present invention is to provide a method to form dual-port DRAM using available shallow trench isolation (STI) trenches to form trench capacitors.
A yet further object of the present invention is to provide a dual-port DRAM cell having a small layout area and excellent performance.
A yet further object of the present invention is to provide dual-port DRAM capability in a system on chip (SOC) integrated circuit device.
In accordance with the objects of this invention, a method to form DRAM cells in an integrated circuit device is achieved. The method comprises providing a substrate. A plurality of STI regions is formed in the substrate. The STI regions comprise trenches in the substrate. The trenches are filled with a first dielectric layer. All of the first dielectric layer is etched away from a first group of the STI regions to form open trenches while leaving the first dielectric layer in a second group of the STI regions. A second dielectric layer is formed overlying the substrate and lining the open trenches. A conductive layer is deposited overlying the oxide layer and completely filling the open trenches. The conductive layer is patterned to define DRAM transistor gat

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