Enhanced cap layer integrity in a high-K metal gate stack by...

Details Enhanced cap layer integrity in a high-K metal gate stack by... Enhanced cap layer integrity in a high-K metal gate stack by...

2011-07-19

2011-07-19

Ghyka, Alexander G (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S299000, C257SE21635, C257SE21616

Reexamination Certificate

active

07981740

ABSTRACT:
When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric cap layers of transistors may have experienced a different process history and may thus require a subsequent adaptation of the final cap layer thickness in one type of the transistors. For this purpose, a hard mask material may be used during a process sequence for forming offset spacer elements in one gate electrode structure while covering another gate electrode structure.

REFERENCES:
patent: 2005/0035409 (2005-02-01), Ko et al.
patent: 2005/0048752 (2005-03-01), Doris et al.
patent: 2008/0102573 (2008-05-01), Liang et al.
Translation of Official Communication from German Patent Office for German Patent Application No. 10 2009 031 110.6 dated May 4, 2010.

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