Embedded stressed nitride liners for CMOS performance...

Details Embedded stressed nitride liners for CMOS performance... Embedded stressed nitride liners for CMOS performance...

2007-10-22

2009-11-10

Pham, Thanh V (Department: 2894)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S791000, C438S142000, C257S170000, C257S018000

Reexamination Certificate

active

07615454

ABSTRACT:
The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 275 MPa to about 450 Mpa.

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