Embedded vertical DRAM cells and dual workfunction logic gates

Details Embedded vertical DRAM cells and dual workfunction logic gates Embedded vertical DRAM cells and dual workfunction logic gates

2000-11-29

2001-07-10

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S248000

Reexamination Certificate

active

06258659

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to processes for the fabrication of embedded vertical DRAM cells and dual workfunction logic gates. In particular, it relates to a novel process for the fabrication of very high-density embedded DRAM and very high-performance support MOSFETs.
A MOSFET is used in forming dynamic random access memory (DRAM). A DRAM circuit will usually include an array of memory cells interconnected by rows and columns, which are known as wordlines and bitlines, respectively. Reading data from, or writing data to, memory cells is achieved by activating selected wordlines and bitlines. Typically, a DRAM memory cell comprises a MOSFET connected to a capacitor. The capacitor includes gate and diffusion regions which are referred to as either drain or source regions, depending on the operation of the transistor.
There are different types of MOSFETs. A planar MOSFET is a transistor where a surface of the channel region of the transistor is generally parallel to the primary surface of the substrate. A vertical MOSFET is a transistor where a surface of the channel region of the transistor is generally perpendicular to the primary surface of the substrate. A trench MOSFET is a transistor where a surface of the channel region of the transistor is not parallel to the primary surface of the substrate and the channel region lies within the substrate. For a trench MOSFET, the surface of the channel region is usually perpendicular to the primary surface, although this is not required.
Specifically, trench capacitors are frequently used with DRAM cells. A trench capacitor is a three-dimensional structure formed into a silicon substrate. This is normally formed by etching trenches of various dimensions into the silicon substrate. Trenches commonly have N+ doped polysilicon as one plate of the capacitor (a storage node). The other plate of the capacitor is formed usually by diffusing N+ dopants out from a dopant source into a portion of the substrate surrounding the lower part of the trench. Between these two plates, a dielectric layer is placed which thereby forms the capacitor.
To prevent carriers from traveling through the substrate between the adjacent devices, e.g. capacitors, device isolation regions are formed between adjacent semiconductor devices. Generally, device isolation regions take the form of thick field oxide regions extending below the surface of the semiconductor substrate. The most common early technique for forming a field oxide region is the local oxidation of silicon (“LOCOS”) technique. LOCOS field oxidation regions are formed by first depositing a layer of silicon nitride (“nitride”) on the substrate surface and then selectively etching a portion of the silicon nitride layer to form a mask exposing the substrate where the field oxidation will be formed. The masked substrate is placed in an oxidation environment and a thick silicon oxide layer is grown at the regions exposed by the mask, forming an oxide layer extending above and below the surface of the substrate. An alternative to LOCOS field oxidation is the use of shallow trench isolation (“STI”). In STI, a sharply defined trench is formed in the semiconductor substrate by, for example, anisotropic etching. The trench is filled with oxide back to the surface of the substrate to provide a device isolation region. Trench isolation regions formed by STI have the advantages of providing device isolation across their entire lateral extent and of providing a more planar structure. Using improved isolation, continued reductions in size are possible.
Present trends in DRAM technology constantly are driving towards continued scaling of minimum feature size (F) in the DRAM array, and more compact cell layouts (e.g., 7F
2
, 6F
2
). As a result of the need for ever increasing array densities, the scalability of contemporary planar MOSFET cells using trench storage capacitors for F=150 nm and beyond is facing fundamental concerns. Increased P-well doping concentration required to satisfy off-current objectives results in a marked increase in array junction leakage, which degrades retention time. The scalability of the MOSFET, by itself, is driving the paradigm shift towards vertical MOSFET access transistors in the array.
An additional influence towards reduction in minimum feature size and increasing levels of integration is requirements by semiconductor chip customers for products having more and more function on a single silicon chip. For example, embedded DRAM/Logic (EDRAM) products rapidly are gaining popularity.
For memory producers to be competitive in the marketplace, it is required that the DRAM portion of the chip feature very high density (for memory productivity) concurrently with very high performance support MOSFETs. Achieving this combination of objectives is a major challenge to the industry.
SUMMARY OF THE INVENTION
Now, according to the present invention, a novel process has been developed for producing very high-density embedded DRAM/very high-performance logic structures. The process comprises making vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports. The process features the employment of a single block mask and etching level to define the borderless bitline contact in the array in the same operation in forming the gate conductor for the supports. The process also provides for a bitline contact which is self-aligned to the active area (borderless to adjacent Raised Shallow Trench Isolation (RSTI)); and eliminates a Boron-Phospho-Silicate Glass (BPSG) reflow step, reducing the thermal budget and allowing shallower source/drains.


REFERENCES:
patent: 5827765 (1998-10-01), Stengl et al.
patent: 5981332 (1999-11-01), Mandelman et al.
patent: 6150210 (2000-11-01), Arnold

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