Embedded DRAM on silicon-on-insulator substrate

Details Embedded DRAM on silicon-on-insulator substrate Embedded DRAM on silicon-on-insulator substrate

2000-10-12

2002-02-26

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C043S042090, C043S042090, C043S140000, C043S042090

Reexamination Certificate

active

06350653

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to the field of semiconductor devices, and more specifically, to a semiconductor substrate having both bulk semiconductor areas and areas of silicon-on-insulator (“SOI”). The semiconductor substrate further contains embedded dynamic random access memory (“DRAM”) and logic devices, where the DRAM devices have been formed in bulk regions and logic devices have been formed in SOI regions, and where doped polysilicon is used as a mask to form isolation and/or storage trenches in the bulk regions. The invention is also directed to methods of forming the structure thus described.
2. Related Art
Dynamic random access memory, or DRAM, is a type of semiconductor memory in which the information is stored as data bits in capacitors on a metal-oxide-semiconductor (“MOS”) integrated circuit. Each bit is typically stored as an amount of electrical charge in a storage cell consisting of a capacitor and a transistor. Due to charge leakage, the capacitor discharges gradually and the memory cell can lose the information. Therefore, to preserve the information, the memory must be refreshed periodically. Despite this inconvenience, the DRAM is a very popular memory technology because of its high density and consequent low price.
Conventional semiconductor DRAM devices are formed in bulk semiconductive substrate material by implanting a well of either p-type or n-type material in a wafer of either type material. Gates and source/drain diffusions are then manufactured using commonly known processes. These can form devices known as metal-oxide-semiconductor field effect transistors, or MOSFETs. When a given chip uses both p-type and n-type semiconductors, it is known as a complementary metal oxide semiconductor (“CMOS”) chip. Each of these type devices must be electrically isolated from the others in order to avoid electrical shorting of the circuits. A relatively large amount of surface area is needed for the electrical isolation of the various FETs, which is undesirable in the current trends towards overall size reduction and greater integration. Additionally, parasitic paths and junction capacitance problems may be present because of the source/drain diffusions' physical proximity to other FETs and to the bulk substrate. These problems more frequently arise when trying to scale circuitry down to the sizes necessary for greater circuit density.
Silicon-on-insulator (“SOI”) technology has been increasingly used to alleviate these problems. However, SOI suffers from problems of self-heating, electrostatic discharge susceptibility, low breakdown voltage, and dynamic floating body effects, which in turn present problems for passgate devices and devices requiring tight threshold voltage control. The so-called “floating body effect” occurs when the body of the device is not connected to a fixed potential and, therefore, the device takes on a charge based on the history of the device. The floating body effect greatly affects device reliability.
Some types of semiconductor memory are more susceptible to the floating body effect. For instance, in dynamic random access memory (“DRAM”) the information is stored in capacitors in an MOS circuit. Therefore, in DRAM, the floating body effect is especially detrimental since it is critical that the associated transistor stays in an “off” condition to prevent charge leakage from the storage capacitor.
Another problem specific to SOI is that the formation of large value capacitors (e.g., for decoupling applications) is very difficult because a specific purpose of SOI is to reduce junction capacitance. Since SOI diffusion capacitance is small relative to bulk technologies, use of diffusions to obtain decoupling capacitance is impractical with SOI.
Accordingly, a need exists for combining areas of SOI for high performance support devices, with adjacent bulk devices for low leakage memory arrays.
SUMMARY OF THE INVENTION
The present invention discloses a bulk/SOI hybrid semiconductor substrate which contains embedded dynamic random access memory (“DRAM”) and logic devices, and wherein the DRAM devices have been formed in bulk regions and the logic devices have been formed in SOI regions, and where doped polysilicon is used as a mask to form isolation and/or storage trenches in the bulk regions. The invention is also directed to methods of forming the structure thus described.
The present invention provides a semiconductor apparatus comprising: a single crystalline substrate having a substantially planar surface; a first surface area on the planar surface having a semiconductor-on-insulator region; a second surface area on the planar surface being a single crystalline bulk region; embedded logic devices formed in the silicon-on-insulator region; embedded memory devices formed in the single crystalline bulk region; and storage trenches within the bulk region.
The present invention additionally provides a semiconductor apparatus comprising: a single crystalline substrate having a substantially planar surface; a first surface area on the planar surface having a semiconductor-on-insulator region; a second surface area on the planar surface being a single crystalline bulk region having substantially the same crystalline structure as the planar surface; at least one deep trench in the single crystalline bulk region; an array of memory devices constructed in the single crystalline bulk region; at least one logic device constructed on the first surface area on the planar surface; electrical contacts connected to each memory and logic device; and an insulative material deposited upon the first surface area.
The present invention also discloses a method for forming a semiconductor apparatus, comprising the steps of: providing a single crystalline substrate having a substantially planar surface; forming a silicon-on-insulator region on a first surface area of said planar surface; forming a single crystalline bulk region on a second surface area of said planar surface; forming embedded logic devices in said silicon-on-insulator region; forming embedded memory devices in said single crystalline bulk region; and forming trenches in the single crystalline bulk region.


REFERENCES:
patent: 4037243 (1977-07-01), Hoffman et al.
patent: 4499558 (1985-02-01), Mazin et al.
patent: 5517038 (1996-05-01), Maeda et al.
patent: 5532957 (1996-07-01), Malhi
patent: 5547886 (1996-08-01), Harada
patent: 5703522 (1997-12-01), Arimoto et al.
patent: 5740099 (1998-04-01), Tanigawa
patent: 5808336 (1998-09-01), Miyawaki
patent: 5894152 (1999-04-01), Jaso et al.
patent: 5959927 (1999-09-01), Yamagata et al.
patent: 5991225 (1999-11-01), Forbes et al.
Sunouchi et al., “240 nm Pitch 4GDRAM Array MOSFET Technologies withX-ray Lithography”, 1996 IEEE, pp. 601-604, IEDM 96.*
Lee et al., “Performance improvements in high density DRAM application using.15/spl mu/m body contacted SOI technology”,SOI Conference 2000 IEEE International, , 76-77, Oct. 2-5, 2000.*
Kim et al., Advanced Integration technology for a high ly scalable SOI DRAM with silicon on capacitors, Electron Devices Meeting, 1996, International, 605-608, Dec. 8-11, 1996.*
IBM Technical Disclosure Bulletin—Selective SOI and Integration with Planar Oxide Isolated Bulk Devices, Oct. 1992, pp 196-197.

Affiliated with

Also associated with

Rating

Embedded DRAM on silicon-on-insulator substrate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Embedded DRAM on silicon-on-insulator substrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Embedded DRAM on silicon-on-insulator substrate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2959281